It should be an identical patch except for the commit message. Do you
want me to send out a new one? Either way is fine with me.
~Haohui
On Tue, May 10, 2022 at 10:14 PM Alex Deucher wrote:
>
> On Tue, May 10, 2022 at 6:53 AM Haohui Mai wrote:
> >
> > Hi Alex,
> >
&g
Hi Alex,
Is there anything open before it can be merged?
Thanks,
Haohui
On Mon, May 9, 2022 at 10:48 PM Alex Deucher wrote:
>
> On Fri, May 6, 2022 at 10:30 PM Haohui Mai wrote:
> >
> > What about
> >
> > Setting the HALT bit of SDMA_F32_CNTL in all paths b
What about
Setting the HALT bit of SDMA_F32_CNTL in all paths before programming
the ring buffer of the SDMA engine.
No other changes are required in the patch.
~Haohui
On Fri, May 6, 2022 at 9:36 PM Alex Deucher wrote:
>
> On Fri, May 6, 2022 at 1:11 AM Haohui Mai wrote:
> >
gt;
> > From: Haohui Mai
> >
> > The patch fully deactivates the DMA engine before setting up the ring
> > buffer to avoid potential data races and crashes.
>
> Does this actually fix an issue you are seeing? I don't think it will
> hurt anything, but I also don&#
Ping...
From: ricet...@gmail.com
Sent: Saturday, April 30, 2022 3:34:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: lang...@amd.com ; ckoenig.leichtzumer...@gmail.com
; guchun.c...@amd.com ;
yifan1.zh...@amd.com ; hawking.zh...@amd.com
; Haohui Mai
Subject
Sorry about that. But can you please confirm that the call of
sdma_v5_2_ctx_switch_disable_all() is still required to fully disable
the engine?
Thanks,
Haohui
On Fri, Apr 29, 2022 at 4:32 PM Lang Yu wrote:
>
> On 04/29/ , Haohui Mai wrote:
> > Thanks for pointing it out. The v5 pat
Thanks for pointing it out. The v5 patch added the code back.
~Haohui
On Thu, Apr 28, 2022 at 10:05 PM Lang Yu wrote:
>
> On 04/28/ , Haohui Mai wrote:
> > If I understand correctly, the original code will disable the HALT bit
> > of the register mmSDMA0_F32_CNTL twice o
is the expected behavior?
~Haohui
On Thu, Apr 28, 2022 at 6:27 PM Lang Yu wrote:
>
> On 04/28/ , ricet...@gmail.com wrote:
> > From: Haohui Mai
> >
> > The patch fully deactivates the DMA engine before setting up the ring
> > buffer to avoid potential data races and
ote:
>
> On 04/28/ , Christian König wrote:
> > Adding a few more people to review this.
> >
> > Am 28.04.22 um 04:11 schrieb ricet...@gmail.com:
> > > From: Haohui Mai
> > >
> > > The patch fully deactivates the DMA engine before setting up the ring
ux kernel source.
>
> I haven't double checked, but of hand a few lines look a bit long.
>
> Christian.
>
> Am 27.04.22 um 14:09 schrieb ricet...@gmail.com:
> > From: Haohui Mai
> >
> > The patch fully deactivates the DMA engine before setting up the ring
&g
Great, thanks! I'll work on a patch then.
~Haohui
On Wed, Apr 27, 2022 at 1:57 PM Christian König
wrote:
>
> Am 27.04.22 um 03:53 schrieb Haohui Mai:
> > Hi,
> >
> > I'm looking at the initialization sequences in sdma_v5_2.c. I'm
> > confused on wh
Hi,
I'm looking at the initialization sequences in sdma_v5_2.c. I'm
confused on whether the DMA engine should be activated when updating
the MMIO registers. Some clarifications are highly appreciated.
Here is the background:
* sdma_v5_2_enable() toggles the HALT bit to enable / disable the
async
41 PM Haohui Mai wrote:
>
> This patch fixes the issue where the driver miscomputes the 64-bit
> values of the wptr of the SDMA doorbell when initializing the
> hardware. SDMA engines v4 and later on have full 64-bit registers for
> wptr thus they should be set properly.
>
>
/ 24bits
for the WPTR, where the calls of lower_32_bits() will be removed in a
following patch.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8
3 files changed
Sounds good to me.
Updated the patch for the CIK / SI hardware. I kept the clamping code
to be safe.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8
drivers/gpu
Dropped the changes of older generations.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a
I kept the original clamping for CIK / SI in this patch.
Please let me know if you want to remove them.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8
drivers
Updated the commit messages based on the previous discussion.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4
22 at 7:02 PM Christian König
wrote:
>
> Am 25.04.22 um 11:15 schrieb Haohui Mai:
> > Computing the address of the doorbell should be done before instead of after
> > separating the 64-bit address into the higher and lower half. The
> > current code sets the MMIO registers incor
Thanks for the prompt reviews. Here is the updated patch.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 9426e252d8aa
Computing the address of the doorbell should be done before instead of after
separating the 64-bit address into the higher and lower half. The
current code sets the MMIO registers incorrectly if the address of the
doorbell is above 1G.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu
The gfx_v10_0_ring_test_ib() function uses 20 bytes instead of 16
bytes during the test. The patch sets the size of the allocation to be
4-byte larger to match the actual usage.
Signed-off-by: Haohui Mai
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1
22 matches
Mail list logo
