RE: [PATCH 3/3] drm/amdgpu/vcn: Use offsets local to VCN/JPEG in VF

[AMD Official Use Only - AMD Internal Distribution Only] Ping for this series... Thanks, Jane -Original Message- From: Jane Jian Sent: Tuesday, July 16, 2024 4:47 PM To: Lazar, Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org; Jian, Jane Subject: [PATCH 3/3] drm

RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

ll. 2. currently we only covered gpu flush tlb path since blocking issues, later I will submit part 2 that covers the normalization for all sriov read/write cases(not only KIQ code. Thanks, Jane -Original Message- From: Christian König Sent: Monday, June 24, 2024 7:58 PM To: Jian, Jane ; Lazar,

RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

. Thanks, Jane -Original Message- From: Christian König Sent: Monday, June 24, 2024 5:35 PM To: Jian, Jane ; Lazar, Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov in TLB flush

RE: [PATCH] drm/amdgpu: part I - normalize registers as local xcc to read/write under sriov in TLB

[AMD Official Use Only - AMD Internal Distribution Only] Ping for this. Thanks, Jane -Original Message- From: Jane Jian Sent: Thursday, June 20, 2024 12:32 AM To: Lazar, Lijo Cc: amd-gfx@lists.freedesktop.org; Jian, Jane Subject: [PATCH] drm/amdgpu: part I - normalize registers as

RE: [PATCH] drm/amdgpu: part I - normalize registers as local xcc to read/write under sriov in TLB

: Jane Jian Sent: Wednesday, June 19, 2024 5:55 PM To: Lazar, Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org; Jian, Jane Subject: [PATCH] drm/amdgpu: part I - normalize registers as local xcc to read/write under sriov in TLB [WHY] sriov has the higher bit violation when

RE: [PATCH] drm/amdgpu: normalize registers as local xcc to read/write under sriov

[AMD Official Use Only - AMD Internal Distribution Only] Ping on this... Thanks, Jane -Original Message- From: Jane Jian Sent: Monday, June 17, 2024 6:11 PM To: Lazar, Lijo ; Chang, HaiJun ; Zhao, Victor Cc: amd-gfx@lists.freedesktop.org; Jian, Jane Subject: [PATCH] drm/amdgpu

RE: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID

[Public] Hi Guchun, Per Alex's suggestion, we would better add a check for new vcn0 IP version, which is a version only owned by sriov and a way that I originally did, how do you think? Thanks, Jane From: Deucher, Alexander Sent: Tuesday, November 23, 2021 11:03 PM To: Jian, Jane ; am

RE: [PATCH] drm/amdgpu: drop psp ih programming for sriov guest on navi

[AMD Official Use Only - Internal Distribution Only] Reviewed by Jane Jian -Original Message- From: Hawking Zhang Sent: Tuesday, December 22, 2020 7:11 PM To: amd-gfx@lists.freedesktop.org; Sierra Guiza, Alejandro (Alex) ; Jian, Jane Cc: Zhang, Hawking Subject: [PATCH] drm/amdgpu

RE: [PATCH] drm/amdgpu: correct the gpu reset handling for job != NULL case

[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Jane Jian -Original Message- From: Quan, Evan Sent: Thursday, October 15, 2020 3:03 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Jian, Jane ; Quan, Evan Subject: [PATCH] drm/amdgpu: correct the gpu

RE: [PATCH] drm/amd/powerplay: skip judging if baco support for Arcturus sriov

Cc: Jian, Jane ; Min, Frank Subject: [PATCH] drm/amd/powerplay: skip judging if baco support for Arcturus sriov since for sriov, baco happens on host side, no need and meaning to judge is baco. also, since kiq reads strap0 in here, if kiq is not ready or gpu reset(kiq resume) happens after