[PATCH v2] drm/amdkfd: Initialize kfd_gpu_cache_info for KFD topology

to be filled in by lower-level functions. Fixes: 04756ac9a24c ("drm/amdkfd: Add cache line sizes to KFD topology") Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drive

[PATCH] drm/amdkfd: Initialize kfd_gpu_cache_info for KFD topology

to be filled in by lower-level functions. Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3df2a8ad86fb..67c1e7f84750 100644

[PATCH] drm/amdkfd: Add cache line sizes to KFD topology

The KFD topology includes cache line size, but we have not been filling that information out unless we are parsing a CRAT table. Fill in this information for the devices where we have cache information structs, and pipe this information to the topology sysfs files. Signed-off-by: Joseph

[PATCH] drm/amdgpu: Enable translate_further to extend UTCL2 reach

Enable translate_further on Arcturus and Aldebaran server chips in order to increase the UTCL2 reach from 8 GiB to 64 GiB, which is more in line with the amount of framebuffer DRAM in the devices. Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++ 1 file changed

[PATCH] drm/amdgpu: Add MODE register to wave debug info in gfx11

All other chips, from gfx6-gfx10, now include the MODE register at the end of the wave debug state. This appears to have been missed in gfx11, so this patch adds in MODE to the debug state for gfx11. Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 + 1 file

[PATCH] umr: print MODE register as part of wave state

The MODE register contains detailed per-wave information, but UMR skipped printing it. This patch adds the ability to print each wave's MODE register as part of the wave scan operation, and prints the MODE register's sub-fields as part of the deeper print option. Signed-off-by: Joseph Greathouse

[PATCH 3/3] drm/amdkfd: Spread out XGMI SDMA allocations

Avoid hotspotting of allocations of SDMA engines from the XGMI pool by making each process attempt to allocate engines starting from the engine after the last one that was allocated. Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 8 +++- drivers

[PATCH 2/3] drm/amdgpu: Use SDMA1 for buffer movement on Aldebaran

Aldebaran should not use SDMA0 for buffer funcs such as page migration. Instead, we move over to SDMA1 for these features. Leave SDMA0 in charge for all other existing chips to avoid any possibility of regressions. Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8

[PATCH 1/3] drm/amdkfd: Allocate SDMA engines more fairly

at any time, but after the first SDMA allocation request from a process, the resulting engine must be from SDMA1 or above. This patch handles this case as well. Signed-off-by: Joseph Greathouse --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 135 +- drivers/gpu/drm/amd/amdkfd

[PATCH] drm/amdgpu: Put MODE register in wave debug info

Add the MODE register into the per-wave debug information. This register holds state such as FP rounding and denorm modes, which exceptions are enabled, and active clamping modes. Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + drivers/gpu/drm/amd/amdgpu

[PATCH v2 umr 3/3] Enhance printing of page tables in AI+

) properly indent the next layer of the print. Prints remaining fields from the PTE and PDE printouts, such as read/write/execute bits and MTYPE from PTE. v2: Correctly handle printing translate-further PTEs Signed-off-by: Joseph Greathouse --- src/lib/read_vram.c | 184

[PATCH umr 2/3] Generalize decoding of PDEs and PTEs in AI+

-by: Joseph Greathouse --- src/lib/read_vram.c | 187 ++-- 1 file changed, 109 insertions(+), 78 deletions(-) diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c index 049acd4..2998873 100644 --- a/src/lib/read_vram.c +++ b/src/lib/read_vram.c @@ -317,6 +317,104

[PATCH umr 3/3] Enhance printing of page tables in AI+

) properly indent the next layer of the print. Prints remaining fields from the PTE and PDE printouts, such as read/write/execute bits and MTYPE from PTE. Signed-off-by: Joseph Greathouse --- src/lib/read_vram.c | 184 ++-- 1 file changed, 127 insertions

[PATCH umr 1/3] Improve handling of non-standard page tables in AI+

sizes. Signed-off-by: Joseph Greathouse --- src/lib/read_vram.c | 199 ++-- 1 file changed, 153 insertions(+), 46 deletions(-) diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c index efcd081..049acd4 100644 --- a/src/lib/read_vram.c +++ b/src/lib

[PATCH] Update NV SIMD-per-CU to 2

amount of work to each SIMD. Signed-off-by: Joseph Greathouse Change-Id: I94021ca71363a3d27330b2fda8e6acaac258017e --- drivers/gpu/drm/amd/include/navi10_enum.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/navi10_enum.h b/drivers/gpu/drm/amd

[PATCH] drm/amdgpu: Copy MEC FW version to MEC2 if we skipped loading MEC2

on MEC2. Leaving these MEC2 entries blank breaks our ability to version-check enables and workarounds. Signed-off-by: Joseph Greathouse Change-Id: Id6f672fc69452abd6ff41821a5f2240037048a6f --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm

[PATCH] drm/amdkfd: Add Arcturus GWS support and fix VG10

Add support for GWS in Arcturus, which needs MEC2 firmware #48 or above. Fix the MEC2 version check for Vega 10 GWS support, since Vega 10 firmware adds 0x8000 to the actual firmware revision. We were previously declaring support where it did not exist. Signed-off-by: Joseph Greathouse Change-Id

[PATCH] drm/amdkfd: Update hardware scheduling time quanta

ues in a CP. Signed-off-by: Joseph Greathouse Change-Id: I5f46d268a82eb08e75bfaf0aed5333c3341b64bd --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c| 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c| 2 +- drivers/gpu/drm/

[PATCH] drm/amdgpu: Reconfigure ULV for gfx9 server SKUs

SDMA ULV can benefit low-power modes, but can sometimes cause latency increases in small SDMA transfers. Server SKUs have a different trade-off space in this domain, so this configures the server SKUs' ULV hysteresis times differently than consumer SKUs'. Signed-off-by: Joseph Greathouse Change

[PATCH v2] drm/amdkfd: Put ASIC revision into HSA capability

the hardware is maximum of 4 bits at this time, so put it into 4 of the open bits in the HSA capability. Then user-level software can use this capability information to know -- for each ASIC -- what revision-based things must be done. Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu

[PATCH 1/2] drm/amdgpu: Add KFD interface to get ASIC revision

KFD need sto surface the ASIC revision in certain circumstances. amdgpu already has this floating around, so add in an amdgpu_amdkfd interface function to pull it over to KFD. Signed-off-by: Joseph Greathouse Change-Id: I745196129d65e1d0d4349f8d3b3f828df961a603 --- drivers/gpu/drm/amd/amdgpu

[PATCH 2/2] drm/amdkfd: Put ASIC revision into HSA capability

the hardware is maximum of 4 bits at this time, so put it into 4 of the open bits in the HSA capability. Then user-level software can use this capability information to know -- for each ASIC -- what revision-based things must be done. Signed-off-by: Joseph Greathouse Change-Id

[PATCH v2] drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus

patch title to list component Change-Id: I4f80d6bc0c795b62e1f71bbd09d063b7f75249fd Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 + .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h| 6 -- 2 files changed, 21 insertions(+), 2 deletions

[PATCH] Enable DISABLE_BARRIER_WAITCNT for Arcturus

: I4f80d6bc0c795b62e1f71bbd09d063b7f75249fd Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 17 + .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h| 6 -- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd

[PATCH v2] drm/amdkfd: Enable GWS based on FW Support

: Ife6833c2d571f5e7fe0726f9340649ce0ef10443 Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 +++-- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 40 ++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1

[PATCH] drm/amdkfd: Enable GWS based on FW Support

-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 +++-- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 40 ++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c

[PATCH 2/3] drm/amdgpu: add defines for DF and TCP Hashing

in preparation for a future patch which will use them. Change-Id: Ia405ee9aeec6fc22303a7376ec3d714e3f93af1d Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h | 3 +++ drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h | 8 drivers/gpu/drm/amd

Rework DF to prepare for VBIOS that turns on channel hashing

When we start receiving Arcturus VBIOS that turns on channel hashing in the data fabric, we need to make sure that the texture cache's channel hashing setting match up. To do this, we query the DF's settings and cache them in adev, then mirror them into the cache confirmation on init. This

[PATCH 3/3] drm/amdgpu: Match TC hash settings to DF settings

configured DF, then matches the TC hash configuration bits to do the same thing. Change-Id: I01e9e73ce6c89ea340925b4a1b895889ac152ec3 Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/df_v1_7.c | 3 +++ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 28 +++ drivers/gpu/drm

[PATCH 1/3] drm/amdgpu: Create generic DF struct in adev

table, but new stuff will be added soon. Change-Id: I0359344297a740782efd35e902f9638bc9e67da8 Signed-off-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 29 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_df.h | 62 drivers/gpu/drm/amd/amdgpu