Using kzalloc() results in about 50% memory fragmentation, therefore
use the slab allocator to reproduce memory fragmentation.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 26 -
drivers/gpu/drm
This will add the following bechmark dump for the amdgpu driver
performance tunning.
1. AMDGPU hardware configuration.
2. AMDGPU engine clock setting
3. AMDGPU link speed
4. AMDGPU momory move performance
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1
Export the firmware info in the benchmark metrics.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 5 +
3 files changed, 10 insertions(+), 1 deletion
Add the amdgpu buffer object move speed metrics.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 78 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
3 files changed, 61 insertions
.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 -
3 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm
Fix the KGQ fallback function name, as this will
help differentiate the failure in the KCQ enablement.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers
Currently, GPU resets can now be performed successfully on the Raven
series. While GPU reset is required for the S3 suspend abort case.
So now can enable gpu reset for S3 abort cases on the Raven series.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 45
Currently, GPU resets can now be performed successfully on the Raven
series. While GPU reset is required for the S3 suspend abort case.
So now can enable gpu reset for S3 abort cases on the Raven series.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 45
In the suspend abort cases, the gfx power rail doesn't turn off so
some GFXDEC registers/CSB can't reset to default value and at this
moment reinitialize GFXDEC/CSB will result in an unexpected error.
So let skip those program sequence for the suspend abort case.
Signed-off-by: Prike Liang
In the s3 suspend abort case some type of gfx9 power
rail not turn off from FCH side and this will put the
GPU in an unknown power status, so let's reset the gpu
to a known good power state before reinitialize gpu
device.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 22
In the pm abort case the gfx power rail not turn off from FCH side and
this will lead to the gfx reinitialized failed base on the unknown gfx
HW status, so let's reset the gpu to a known good power state.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5
In the PM abort cases, the gfx power rail doesn't turn off so
some GFXDEC registers/CSB can't reset to default vaule. In order
to avoid unexpected problem now need skip to program GFXDEC registers
and bypass issue CSB packet for PM abort case.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd
In the PM abort cases, the gfx power rail doesn't turn off so
some GFXDEC registers/CSB can't reset to default vaule. In order
to avoid unexpected problem now need skip to program GFXDEC registers
and bypass issue CSB packet for PM abort case.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd
In the pm abort case the gfx power rail not turn off from FCH side and
this will lead to the gfx reinitialized failed base on the unknown gfx
HW status, so let's reset the gpu to a known good power state.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
drivers
Fix the amdgpu runpm dereference usage count.
Signed-off-by: Prike Liang
---
v2: remove goto clause and return directly(Alex)
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b
Fix the amdgpu runpm dereference usage count.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index
in the amdgpu runpm usage
dereference.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 15 +++
3 files changed, 25 insertions(+), 1 deletion(-)
diff
Fix the amdgpu runpm dereference usage count.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b
Needn't set aggregated doorbell for map queue and remove
the dead code.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 --
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4
2 files changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b
There's need a check on the GPU error state before save and restore
GPU device config space.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu
Now the SDMA firmware support SDMA MGCG properly,
so let's enable it from the driver side.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/nv.c| 6 --
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 27 +-
2 files changed, 30 insertions(+), 3 deletions
Now the SDMA firmware support SDMA MGCG properly,
so let's enable it from the driver side.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/nv.c| 6 --
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
Cc: sta...@vger.kernel.org # 6.0
Fixes: f8f4e2a51834 ("drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.")
Signed-off-by: Prike Liang
---
-v2: change the name sdma_v4_0_gfx_stop() to sdma_v4_0_gfx_enable() (Lijo)
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 24 +++--
Cc: sta...@vger.kernel.org # 6.0
Fixes: f8f4e2a51834 ("drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.")
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/g
In the S2idle suspend/resume phase the gfxoff is keeping functional so
some IP blocks will be likely to reinitialize at gfxoff entry and that
will result in failing to program GC registers.Therefore, let disallow
gfxoff until AMDGPU IPs reinitialized completely.
Signed-off-by: Prike Liang
In the S2idle suspend/resume phase the gfxoff is keeping functional so
some IP blocks will be likely to reinitialize at gfxoff entry and that
will result in failing to program GC registers.Therefore, let disallow
gfxoff until AMDGPU IPs reinitialized completely.
Signed-off-by: Prike Liang
Update the gfx1037 L1/L2/L3 cache setting.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 960046e43b7a
This dummy cache info will enable kfd base function support.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +--
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd
Correct the isa version for handling KFD test.
Fixes: 7c4f4f197e0c ("drm/amdkfd: Add GC 10.3.6 and 10.3.7 KFD definitions")
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
On the GC 10.3.7 platform the initial MEC release version #3 can support
atomic operation,so need correct and set its MEC atomic support version to #3.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
On the psp13 series use ta_firmware_header_v2_0 and the asd firmware
was buildin ta, so needn't request asd firmware separately.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
Without MMHUB clock gating being enabled then MMHUB will not disconnect
from DF and will result in DF C-state entry can't be accessed during S2idle
suspend, and eventually s0ix entry will be blocked.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 10 ++
1 file
Without MMHUB clock gating being enabled then MMHUB will not disconnect
from DF and will result in DF C-state entry can't be accessed during S2idle
suspend, and eventually s0ix entry will be blocked.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 9 +
1 file
Enable gfx1037 clock counter retrieval function for
KFDPerfCountersTest.ClockCountersBasicTest.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu
Disable xnack on the isa gfx10.3.6.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index e1635a3f2553..a66a0881a934 100644
--- a/drivers
Enable gfxoff routine for GC 10.3.7.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu
Enable gfx power gating for GC 10.3.7.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
drivers/gpu/drm/amd/amdgpu/nv.c| 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu
This will enable the following block clock gating.
- MC
- SDMA
- HDP
- ATHUB
- IH
- VCN/JPEG
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/nv.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm
Enable gfx cg gate/ungate control for GC 10.3.7.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 90158289cd30..fd7ded7799e2 100644
Set mode2 reset support for MP1 13.0.8.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5f375f3430e1..f414b7ca0ab7 100644
--- a/drivers/gpu/drm/amd/amdgpu
This will enable the following gfx clock gating.
- Fine clock gating
- Medium Grain clock gating
- 3D Coarse clock gating
- Coarse Grain clock gating
- RLC/CP light sleep clock gating
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/nv.c | 10 +-
1 file changed, 9 insertions
There's always miss the SMU feature enabled checked in the NPI phase,
so let validate the SMU feature enable message directly rather than
add more and more MP1 version check.
Signed-off-by: Prike Liang
Signed-off-by: Lijo Lazar
---
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 12
There's always miss the SMU feature enabled checked in the NPI phase,
so let validate the SMU feature enable message directly rather than
add more and more MP1 version check.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 28 ++
1 file changed, 6
The TMZ is disabled by default and enable TMZ option
for the IP discovery based asic will help on the TMZ
function verification.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b
The TMZ is disabled by default and enable TMZ option
for the IP discovery based asic will help on the TMZ
function verification.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b
In some APU project we needn't always assign flags to identify each other,
so we may not need return an error.
Change-Id: I92c1acb9ffbdba7e9a68469163911801db262412
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++
1 file changed, 2
In the s0ix entry need retain gfx in the gfxoff state,so here need't
set gfx cgpg in the S0ix suspend-resume process. Moreover move the S0ix
check into SMU12 can simplify the code condition check.
Signed-off-by: Prike Liang
---
v1->v2:
- Move s0ix check into SMU12.
---
drivers/gpu/drm/amd
In the s0ix entry need retain gfx in the gfxoff state,we don't
disable gfx cgpg in the suspend so there is also needn't enable
gfx cgpg in the s0ix resume.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
and add GPU hive case check for
GPU reset.
v3: Some dGPU reset method not support at the early resume time and
temprorary skip the dGPU case.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd
and add GPU hive case check for
GPU reset.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7d4115d..3fcd90d 100644
Do ASIC reset at the moment Sx suspend aborted behind of amdgpu suspend
to keep AMDGPU in a clean reset state and that can avoid re-initialize
device improperly error.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
In the s2idle stress test sdma resume fail occasionally,in the
failed case GPU is in the gfxoff state.This issue may introduce
by FSDL miss handle doorbell S/R and now temporary fix the issue
by forcing exit gfxoff for sdma resume.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu
In the s2idle stress test sdma resume fail occasionally,in the
failed case GPU is in the gfxoff state.This issue may introduce
by FSDL miss handle doorbell S/R and now temporary fix the issue
by forcing exit gfxoff for sdma resume.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu
During system hibernation suspend still need un-gate gfx CG/PG firstly to
handle HW
status check before HW resource destory.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
t;drm/amdgpu: update amdgpu device suspend/resume
sequence for s0i3 support")
Signed-off-by: Alex Deucher
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_dr
In the renoir there is no need GpuChangeState message set to exit gfxoff in the
s0i3 resume since
mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1
The gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 18 +-
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
the SDMA
hang.
- Need handle the GPU reset path during amdgpu device suspend.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
add amdgpu_acpi_is_s0ix_supported() to check the platform
whether support s0i3.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 14 ++
2 files changed, 16
The new amdgpu_gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.
Signed-off-by: Prike Liang
Acked-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
add amdgpu_acpi_is_s0ix_supported() to check the platform
whether support s0i3.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 14 ++
2 files changed, 16
update amdgpu device suspend sequence for gpu reset during s0i3 enable.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu
the SDMA
hang.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu
The gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 +++
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10
The new amdgpu_gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.
Signed-off-by: Prike Liang
Acked-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
the SDMA
hang.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu
update amdgpu device suspend sequence for gpu reset during s0i3 enable.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu
add amdgpu_acpi_is_s0ix_supported() to check the platform
whether support s0i3.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 14 ++
2 files changed, 16
The new amdgpu_gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.
Signed-off-by: Prike Liang
Acked-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
Update the smu12_driver_if.h header to follow the pmfw release.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/smu12_driver_if.h| 40 ++
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay
When the amdgpu in the suspend/resume loop need notify the dpm disabled,
otherwise the smu table will be uninitialize and result in resume failed.
Signed-off-by: Prike Liang
Tested-by: Mengbing Wang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 ++-
1 file changed, 6 insertions(+), 1
Unify set device CGPG to ungate state before enter poweroff or reset.
Signed-off-by: Prike Liang
Tested-by: Mengbing Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd
instead of RLC safe mode guard.
Signed-off-by: Prike Liang
Tested-by: Mengbing Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index
Update the smu12_driver_if.h header to follow the pmfw release.
Signed-off-by: Prike Liang
---
.../gpu/drm/amd/powerplay/inc/smu12_driver_if.h| 42 ++
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
b
As the pmfw hasn't exported the interface of SMU feature
mask to APU SKU so just force on all the features to driver
inquired interface at early initial stage.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 12
1 file changed, 12 insertions(+)
diff
The system will be hang up during S3 as SMU is pending at GC not
respose the register CP_HQD_ACTIVE access request and this issue
can be fixed by adding RLC safe mode guard before each HQD
map/unmap retrive opt.
Signed-off-by: Prike Liang
Tested-by: Mengbing Wang
---
drivers/gpu/drm/amd/amdgpu
There will be a coverity warning because min and max are both unsigned.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export
fclk frequency to user usage.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a
reverse
dpm clock layout and a zero frequency dpm level as following case.
cat pp_dpm_mclk
0: 1200Mhz
1: 1200Mhz
2: 800Mhz
3: 0Mhz
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2
SMU12 not support WORKLOAD_DEFAULT_BIT and WORKLOAD_PPLIB_POWER_SAVING_BIT.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd
The mutex for procting SMU during hw_init was removed as system
will be deadlock when smu_populate_umd_state_clk try get SMU mutex.
Therefore need remove the residual mutex from failed path.
Change-Id: Id8019c01b9496c067efda4817a46983e4da3b6e4
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd
Change-Id: I1f071e465c97f70048df5b24466bc7e225833c7f
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index edd1da6..0be2845 100644
Change-Id: Ib050c8cf0c2c5af4c1f747cf596860f9be01a2d3
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c| 1 +
drivers/gpu/drm/amd
Use SMU firmware version to indentify the raven1 refresh device and
then load homologous RLC FW.
Change-Id: I7aaa67d8b59cfec03355d9199f7fb2c30ce39856
Signed-off-by: Prike Liang
Suggested-by: Huang Rui
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12
Use SMU firmware version to indentify the raven1 refresh device and
then load homologous RLC FW.
Change-Id: I7aaa67d8b59cfec03355d9199f7fb2c30ce39856
Signed-off-by: Prike Liang
Suggested-by: Ray Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++-
drivers/gpu/drm/amd/amdgpu
From: Chengming Gui
add gfxoff_state_changed_by_workload to control gfxoff
when set power_profile_mode
Signed-off-by: Chengming Gui
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 31 ---
As the PG was setted by each IP block durinng IP early init thus
remove the unused phm_enable_clock_power_gatings related funcs.
Change-Id: I4d2858f35aaf61ab6457cff3f73409726e52c980
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 9 -
drivers/gpu
87 matches
Mail list logo
