AUX_RET_ERROR_HPD_DISCON detected
on the first sideband message.
Cc: sta...@vger.kernel.org # 4.18+
Signed-off-by: Fangzhi Zuo
Acked-by: Solomon Chiu
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 8
From: Aric Cyr
This version brings along following fixes:
- Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others
- Add register offsets of NBI and DCN.
- Improvement of ALPM
- Removing assert statement for Linux DM
- Re-implementing ARGB16161616 pixel format
Acked-by: Solomon Chiu
Signed
Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Rodrigo Siqueira
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/displ
-by: Solomon Chiu
Signed-off-by: Samson Tam
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 32 +--
.../gpu/drm/amd/display/dc/inc/core_types.h | 27
2 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Aurabindo Pillai
[Why]
Add a field to store the NBIO IP offset for use with runtime offset
calculation
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
Signed-off-by: Aurabindo Pillai
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers
her runtime or compile time initialization of offsets.
The computation of offset is done for registers all at once during
driver load and hence it does not introduce any performance overhead
during normal operation.
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
Signed-off-by: Harry Wentl
From: Charlene Liu
[why]
insert log for debug use.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
Tested-by: Daniel Wheeler
---
.../drm/amd/display/dc/bios/bios_parser2.c| 30 +++
1 file changed, 30 insertions(+)
diff --git
From: Wayne Lin
[Why & How]
There is chance we change dc state while calling dc_link_detect().
As the result of that, grab the dm.dc_lock before detecting link.
Reviewed-by: Hersen Wu
Acked-by: Solomon Chiu
Signed-off-by: Wayne Lin
Tested-by: Daniel Wheeler
---
.../gpu/drm/amd/dis
for
dcn10/20/30.
Reviewed-by: Reza Amini
Acked-by: Solomon Chiu
Signed-off-by: Wellenreiter Ethan
Tested-by: Daniel Wheeler
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
From: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a0812849794e..1dca016b5782 100644
req in HW according
to unbounded req enablement output from DML, as opposed to DML input
Second, port in DML1 update which disables unbounded req in some
scenarios to fix an issue with poor stutter performance
Reviewed-by: Nevenko Stupar
Reviewed-by: Dmytro Laktyushkin
Acked-by: Solomon Chiu
From: Chris Park
[Why]
Status flags definition is reduced to read
less bytes in SCDC transaction for status update.
[How]
Reduce definition of reserved bytes from 3 to 1
for status update.
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd
bandwidth. Remove
the reference of verified link cap during enable link process and
use link config in pipe ctx instead.
Reviewed-by: George Shen
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_debug.c| 2 +
drivers/gpu/drm/amd/display/dc/core
From: Ilya Bakoulin
[Why]
Black screen encountered when disabling Freesync through OSD on some
displays.
[How]
Set the should_disable flag when new top pipe has no plane state to
ensure that pipes get cleaned up.
Reviewed-by: Chris Park
Acked-by: Solomon Chiu
Signed-off-by: Ilya Bakoulin
config.enable_windowed_mpo_odm to true when we have the
debug.enable_single_display_2to1_odm_policy set to true.
Don't fail validating ODM with windowed MPO if
config.enable_windowed_mpo_odm is true.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd
d when unplug mst connector.
Reviewed-by: Hersen Wu
Acked-by: Solomon Chiu
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/d
From: Robin Chen
[Why]
Some specific sink is not able to support PSRSU when DSC is turned on.
For this case, fall-back to use PSR1.
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Robin Chen
---
.../amd/display/modules/power/power_helpers.c | 33 ++-
1 file
From: Saaem Rizvi
[WHY]
Assert statements causing several bugs on Linux DM
[HOW]
Removing assert statement for Linux DM
(ASSERT(result == VBIOSSMC_Result_OK)). Also adding
logging statements for setting dcfclk.
Reviewed-by: Gabe Teeger
Acked-by: Solomon Chiu
Signed-off-by: Saaem Rizvi
From: muansari
[WHY]
Needed a helper function for ALPM DPCD initialization
[HOW]
Refactoring to put ALPM initialization in a helper function
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Muhammad Ansari
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27
From: Wesley Chalmers
[WHY]
Certain DP 2.0 modes may fail validation if DP 2.0 is not considered for
ODM combine.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: Wesley Chalmers
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 1 +
1 file changed, 1
Also don't program K1 / K2 = 0xF ever since the field is only
1 / 2 bits wide.
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 27 +--
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../amd/displa
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others
- Add register offsets of NBI and DCN.
- Improvement of ALPM
- Removing assert statement for Linux DM
- Re-implementing ARGB16161616 pixel format
Aric Cyr
wrong resolution with DP/VGA adapter
- Refactor PSR DPCD caps detection
- Set compbuf size to min at prep prevent overbook crb
- lock/un-lock cursor if odm pipe split used
- OVT Update on InfoFrame and Mode Management
Acked-by: Solomon Chiu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display
From: Charlene Liu
[Why]
add debug option to bypass ssinfo from bios.
Reviewed-by: Chris Park
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 ++
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 2
From: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
arent
mode into a separate function.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: George Shen
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 102 +-
1 file changed, 97 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/d
From: Wenjing Liu
[how]
Call to DMUB to retrieve usb c cable ID data from PD firmware.
If cable id is retrieved from DMUB, skip reading cable ID from RX.
Reviewed-by: George Shen
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
at dm_helpers_dp_mst_stop_top_mgr() was
removed by previous patch. Restore it.
Reviewed-by: Jerry Zuo
Acked-by: Solomon Chiu
Signed-off-by: Wayne Lin
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 20 ++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
to DEBUG.
Reviewed-by: Wayne Lin
Acked-by: Solomon Chiu
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
if the SINK_COUNT DPCD register is read more than once.
[How]
To work around the adapter behavior, remove the sink if link is
detected, but EDID cannot be read.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: Ilya
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 16
From: Po Ting Chen
[Why]
To move the PSR DPCD caps detection into detect_edp_sink_caps()
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Po Ting Chen
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 58
er size. When it is to
optimize BW, set compbuf size back to maximum possible size.
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 ++--
.../drm/amd/display/dc/dml/display_m
-by: Dmytro Laktyushkin
Acked-by: Solomon Chiu
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
From: Chris Park
[Why]
Integrate OVT timing from DM to DC logic to update info frame
and mode management to report the resolution to the OS.
[How]
Reflect RID and Frame Rate to AVI InfoFrame Version 5.
Define new Timing Standard for OVT timing.
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* add debug option to bypass ssinfo from bios.
* Refactor fixed VS logic for non-transparent mode
* add cable ID support for usb c connector
* clear remote dc_sink when stop mst
* Ignore Transitional Invalid Link
From: "Leo (Hanghong) Ma"
[Why]
During DQE's promotion test, error appears in dmesg at boot
on dcn3.1;
[How]
Add NULL pointor check for the pointor to the amdgpu_dm_connector;
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Leo (Hanghong) Ma
---
drivers/g
the assignment algorithm is
executed. It should not be necessary for fast state validation.
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
From: "Leo (Hanghong) Ma"
[Why & How]
The codes to blank all dp display have been called many times,
so add a helper in dc_link to make it more concise.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/
dcn3 failure due to dmcbu_abm not created
- Limit display scaling to up to 4k for DCN 3.1
- Add helper for blanking all dp displays
Acked-by: Solomon Chiu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
From: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Hansen
[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers
[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Hansen
---
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 33
From: Nikola Cornij
[why]
The existing limit was mistakenly bigger than 4k for DCN 3.1
Reviewed-by: Zhan Liu
Acked-by: Solomon Chiu
Signed-off-by: Nikola Cornij
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Jake Wang
[Why & How]
Added root clock optimization debug flags for future debugging.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 18 ++
1 file changed, 18 insertions(+)
diff -
From: Charlene Liu
[why]
dc->config.disable_dmcu set to true, but it still need create
dmcub based abm.
[how]
check to dc->caps.dmcub_support check.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 2 +-
From: Aric Cyr
[Why]
3DLUT not updated due to missing condition
[How]
Check if 3DLUT update is needed
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu
From: Qingqing Zhuo
[Why]
Current FPU code for DCN2x is located under dml/dcn2x.
This is not aligned with DC's general source tree
structure.
[How]
Move FPU code for DCN2x to dml/dcn20.
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
Signed-off-by: Qingqing Zhuo
---
drivers/gpu/drm
.
[How]
Since preferred link settings are already considered inside
decide_link_settings, skip the check in override_training_settings
to avoid infinite link training loops.
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core
From: Charlene Liu
[why]
fix NULL pointer in irq_service_dcn201
[how]
initialize proper num of irq source for linu
Reviewed-by: Sung joon Kim
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 +
drivers/gpu/drm/amd/display/dc/dce
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection
DENTIST_DISPCLK_CHG_DONE to ensure display clock
has been update to target value before driver do other clock related
actions.
Reviewed-by: Cyr Aric
Acked-by: Solomon Chiu
Signed-off-by: Dale Zhao
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Anthony Koo
Reviewed-by: Cyr Aric
Acked-by: Solomon Chiu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display
From: Eric Yang
[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlauskas Nicholas
Acked-by: Solomon Chiu
Signed-off-by: Eric Yang
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6
From: Eric Bernstein
Remove code that would skip wait for lock status for Diags
FPGA case
Reviewed-by: Laktyushkin Dmytro
Acked-by: Solomon Chiu
Signed-off-by: Eric Bernstein
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions
Mike
Acked-by: Solomon Chiu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2f3810f0510c..a948f4f48935 100644
--- a/drivers/gpu/drm
are creating a dedicated interface that does the same thing as
remove and add back the display without changing DTM state.
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 64 +--
.../drm/amd/display/modules/inc/mod_hdcp.h| 11 +++-
2
-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 4 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 6 ---
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 -
.../display/modules/hdcp/hdcp1_execution.c| 6 ---
.../display/modules/hdcp
From: Eric Yang
[Why]
Initializing was missing reg offsets for the dmcub test debug registers
causing assert
[How]
Add initialization
Reviewed-by: Kazlauskas Nicholas
Acked-by: Solomon Chiu
Signed-off-by: Eric Yang
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 -
1 file
From: Wyatt Wood
[Why]
Would like to identify the cause of AUX transactions failing
via ETW logs.
[How]
Add ETW logging for AUX failures.
Reviewed-by: Pavic Josip
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8
1 file changed
Martin
Acked-by: Solomon Chiu
Signed-off-by: Mark Morra
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 108 +++--
drivers/gpu/drm/amd/display/dc/dc.h | 118 +++---
drivers/gpu/drm/amd/display/dc/dc_types.h | 81 ++--
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 393
From: Wyatt Wood
[Why]
GPINT commands have the lowest priority in DMCUB, so it's possible
that the command isn't processed in time.
[How]
Add a log to help identify this case.
Reviewed-by: Koo Anthony
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce
From: Mikita Lipski
[why]
For dual eDP when setting the new settings we need to set
command version to DMUB_CMD_PSR_CONTROL_VERSION_1, otherwise
DMUB will not read panel_inst parameter.
[how]
Instead of PSR_VERSION_1 pass DMUB_CMD_PSR_CONTROL_VERSION_1
Reviewed-by: Wood Wyatt
Acked-by: Solomon
From: Victor Lu
[why]
DST_Y_PREFETCH can overflow when DestinationLinesForPrefetch values are
too large due to the former being limited to 8 bits.
[how]
Set the maximum value of DestinationLinesForPrefetch to be 255 * refclk
period.
Reviewed-by: Laktyushkin Dmytro
Acked-by: Solomon Chiu
From: Victor Lu
[why]
IP parameter min_meta_chunk_size_bytes is read for bandwidth
calculations but it was never defined.
[how]
Define min_meta_chunk_size_bytes and initialize value to 256.
Reviewed-by: Laktyushkin Dmytro
Acked-by: Solomon Chiu
Signed-off-by: Victor Lu
---
drivers/gpu/drm
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Guard DST_Y_PREFETCH register overflow in DCN21
* Add missing DCN21 IP parameter
* Fix PSR command version
* Add ETW logging for AUX failures
* Add ETW log to dmub_psr_get_state
* Fixed EdidUtility build errors
*
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Guard DST_Y_PREFETCH register overflow in DCN21
* Add missing DCN21 IP parameter
* Fix PSR command version
* Add ETW logging for AUX failures
* Add ETW log to dmub_psr_get_state
* Fixed EdidUtility build errors
*
-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index d163007e057c..55f3c76823d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu
From: Jake Wang
[Why & How]
Link index doesn't always correspond to the appropriate eDP instance.
We can assume lower link index is a lower eDP instance and set panel
control instance accordingly.
Signed-off-by: Jake Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
---
-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++---
.../display/dc/dce110/dce110_hw_sequencer.c | 9 ++---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 3 +-
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd
Laktyushkin
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
---
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 28 +++
.../dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 28 +++
.../dc/dml/dcn21/display_rq_dlg_calc_21.c | 28 +++
.../
is requested
for either voltage swing or pre-emphasis.
Signed-off-by: Calvin Hou
Signed-off-by: David Galiffi
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
From: Victor Lu
[why]
The amdgpu_dm IRQ handlers are not freed during the IRQ teardown.
[how]
Add function to deallocate IRQ handlers on amdgpu_dm_irq_fini step.
Signed-off-by: Victor Lu
Reviewed-by: Roman Li
Acked-by: Solomon Chiu
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 51
From: Fangzhi Zuo
1. Catch invalid link_rate and link_count settings
2. Call dc interface to overwrite preferred link settings, and wait
until next stream update to apply the new settings.
Signed-off-by: Fangzhi Zuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
.../drm/amd
From: Dmytro Laktyushkin
This is causing a pstate change underflow regression for
unknown reason
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 --
drivers/gpu/drm/amd/display/dc/dcn20
From: Dmytro Laktyushkin
Some hardware revisions do have a max number of lines limitation
not honouring which can cause pstate switch underflow.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
Lin
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 2c9eed78f6df
m DMCUB FW.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 12 -
.../drm/a
From: Dmytro Laktyushkin
The pmfw structs are specific to the asic and should not be
present in base clk_mgr struct
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Yang
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 116 +-
.../display/dc
From: Roman Li
[Why]
Dcn2.1 socclk entries in bandwidth params are not initialized.
They are not used now, but will be needed for dml validation.
[How]
Populate socclk bw params from dpm clock table
Signed-off-by: Roman Li
Reviewed-by: Dmytro Laktyushkin
Acked-by: Solomon Chiu
---
.../drm
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Populate socclk entries for dcn2.1
* hide VGH asic specific structs
* Add kernel doc to crc_rd_wrk field
* revert max lb lines change
* Log DMCUB trace buffer events
* Fix debugfs link_settings entry
* revert
From: Qingqing Zhuo
[Why]
vblank_workqueue is never released.
[How]
Free it upon dm finish.
Signed-off-by: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
1 file changed, 9 insertions(+)
diff --git
should to be 1 again, but dmub fw can’t update the
register to 1 due to the mpll is not off
[How]
Adds an interface to disable accelerated mode bit,
which allows DM to decide to call during driver
disable/unload scenarios.
Signed-off-by: Yao Wang1
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
From: Dmytro Laktyushkin
SOC needs to be updated to the WM set A values before validation
happens.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 17 -
.../drm/amd/display/dc/dcn30
From: Dmytro Laktyushkin
Incorrect variable used, missing initialization during validation.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 1 +
drivers/gpu/drm/amd/display/dc/dml
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index d26472ef1572
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30
From: Anthony Koo
More updates to the comments to better describe the function of
different cmds and parameters in the dmub interface.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 668 ++
1 file
From: "Leo (Hanghong) Ma"
[Why]
We want to have a debugfs interface to enable or disable DMCUB
trace buffer events.
[How]
Add debugfs interface to enable or disable trace buffer events.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Solomon Chiu
---
.../g
From: Atufa Khan
Not all ASICs have same plane capabilities so need to split them
out for proper support handling.
Signed-off-by: Atufa Khan
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce110
5580 #endif
5581
[How]
Fix it with declaration as "static"
Reported-by: kernel test robot
Signed-off-by: Wayne Lin
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
]
Fix above problems.
Signed-off-by: Wayne Lin
Reviewed-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 10 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 ++
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm
From: "Leo (Hanghong) Ma"
[why]
Word "helper" was misspelled as "helpes" in
dm_helpes_dmub_outbox0_interrupt_control function.
[how]
Fix the spelling.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Yongqiang Sun
Acked-by: Solomon Chiu
---
drivers
ked-by: Solomon Chiu
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 34 ++-
1 file changed, 2 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0d3c7e42204f..6a10daec15cc 100
From: Calvin Hou
[Why]
DCN30 needs to correctly program reversed gamma curve, which DCN20
already has.
Also needs to fix a bug that 252-255 values are clipped.
[How]
Apply two fixes into DCN30.
Signed-off-by: Calvin Hou
Reviewed-by: Jun Lei
Reviewed-by: Krunoslav Kovac
Acked-by: Solomon
inputs in 16ths of a bit.
Use dc function to calculate bandwidth from timing, and make dsc bw calculation
a part of dsc.c.
Signed-off-by: Dillon Varone
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h
From: Jun Lei
[Why?]
Many DSC variables and related functions use whole bits for bpp.
[How?]
Change variables and related functions to use 16ths of a bit for bpp.
Signed-off-by: Dillon Varone
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
From: Jake Wang
[How & Why]
Check DC config to determine if there are any eDPs connected. If there
are no eDPs connected, bypass sink detect when querying eDP presence.
Signed-off-by: Jake Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/
masundaram
Reviewed-by: Jun Lei
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 1ee2000ad099..8ba0a9e2d
update
before calling get_cursor_position.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1471
Reported-by: Lyude Paul
Signed-off-by: Anson Jacob
Reviewed-by: Aurabindo Jayamohanan Pillai
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
1 file chan
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