Directly use tbo's start address will miss the domain start offset. Need
to use gpu_offset instead.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd
If a same GPU VM is shared by kfd and graphic operations, we must align
the vm update mode to sdma, or cpu kmap will fail and cause null pointer
issue.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu
The number of kernel queues has impact on the latency under sriov
usecase. So to reduce the latency we set the default num_kcq = 2 under
sriov if not set manually.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Enable mcbp under sriov by default. Asics with soc21 supports mcbp now
so we should set it enabled.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers
From: Pierre-Eric Pelloux-Prayer
Send this patch on behalf of Pierre-Eric.
This achieves the same result as the sequence used in emit_flush_gpu_tlb
but the invalidation is now a single packet instead of the 3 packets
required to implement reg_write_reg_wait.
Signed-off-by: Pierre-Eric
the non_sched bad job's fence during
pre_asic_reset or the clear is not complete.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index
or the clear is not complete.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index faff4a3f96e6..2e549bd50990 100644
Under virtualization guest needs to receive notification from host to
perform reset in some cases. Add nv mailbox irq in soc21.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform
IDLE-SAVE after VF fini. CPG also needs to be active in save command.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 14 ++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 +++-
2 files
In sriov guest side doesn't need init ras feature, so skip it.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index
Temporary disable mes self teset for gc 11.0.3 during gpu_recovery.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu
kiq_hw_fini.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 42 --
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 1174dcc88db5..b477bed40d61
and before kiq fini.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 ++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 41 +++--
3 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 ++
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 47 +++--
3 files changed, 50 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
[Why]
If mes is not dequeued during fini, mes will be in an uncleaned state
during reload, then mes couldn't receive some commands which leads to
reload failure.
[How]
Perform MES dequeue via MMIO after all the unmap jobs are done by mes
and before kiq fini.
Signed-off-by: YuBiao Wang
Hello,
This patch is reviewed by Andrey and Christian and pushed into bringup
temp branch. It need to be cherry-picked to drm-next, too. Does anyone
has any comments on this patch?
Thanks,
Yubiao Wang
[Why]
In amdgpu_cs_ioctl, amdgpu_job_free could be performed ealier if there
is -ERESTARTSYS
[Why]
csb bo is not unpinned in gfx 9. It will lead to pin_count leak on
driver unload.
[How]
Call bo_free_kernel corresponding to bo_create_kernel in
gfx_rlc_init_csb. This will also unify the code path with other gfx
versions.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu
[Why]
For Vega10, disabling gart of gfxhub could mess up KIQ and PSP
under sriov mode, and lead to DMAR on host side.
[How]
Skip writing GMC registers under sriov.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 +---
1 file changed, 14
[Why]
For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP
under sriov mode, and lead to DMAR on host side.
[How]
Skip writing GMC registers under sriov.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 +---
1 file changed
[Why]
For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP under
sriov mode, and lead to DMAR on host side.
[How]
Do not call gmc_gart_disable under sriov but keep vram_unpin to avoid
pin_count leak.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4
Some IP such as SMU need irq_put to perform hw_fini.
So move irq_fini_hw after ip_fini.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm
Send response to host after received the flr notification from host.
Port NV change to vega10.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 2 ++
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
[Why]
In some cases when we unload driver, warning call trace
will show up in vram_mgr_fini which claims that LRU is not empty, caused
by the ttm bo inside delay deleted queue.
[How]
We should flush delayed work to make sure the delay deleting is done.
Signed-off-by: YuBiao Wang
---
drivers
When init failed in early init stage, amdgpu_object has
not been initialized, so hasn't the ttm delayed queue functions.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
carryover happens.
v5: Remove mutex and gfxoff ctrl unused with current timing registers.
Signed-off-by: YuBiao Wang
Acked-by: Horace Chen
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
carryover happens.
Signed-off-by: YuBiao Wang
Acked-by: Horace Chen
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ff7e9f49040e
[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.
[How]
It could be directly read by MMIO.
v2: Add additional check to prevent carryover issue.
v3: Only check for carryover for once to prevent performance issue.
Signed-off-by: YuBiao Wang
Acked-by: Horace
[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.
[How]
It could be directly read by MMIO.
v2: Add additional check to prevent carryover issue.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++--
1 file changed, 11
[Why]
psp ring wptr is not initialized properly in ring_create,
which would lead to psp failure after several gpu reset.
[How]
Set ring_wptr to zero in psp_ring_create.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 1 +
2
[Why]
IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it.
[How]
Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
drivers/gpu/drm/amd/amdgpu/nv.c
[Why]
IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it.
[How]
Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
drivers/gpu/drm/amd/amdgpu/nv.c
[Why]
IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it.
[How]
Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov.
Signed-off-by: YuBiao Wang
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
drivers/gpu/drm/amd/amdgpu/nv.c
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