From: Arindam Nath <arindam.n...@amd.com>
Change History
--
v3:
- add Fixes and CC tags
- add link to Bugzilla
v2: changes suggested by Joerg
- add flush flag to improve efficiency of flush operation
v1:
- The idea behind flush queues is to defer the IOTLB flushing
for d
From: Arindam Nath <arindam.n...@amd.com>
Change History
--
v2: changes suggested by Joerg
- add flush flag to improve efficiency of flush operation
v1:
- The idea behind flush queues is to defer the IOTLB flushing
for domains for which the mappings are no longer valid. We
From: Arindam Nath <arindam.n...@amd.com>
The idea behind flush queues is to defer the IOTLB flushing
for domains for which the mappings are no longer valid. We
add such domains in queue_add(), and when the queue size
reaches FLUSH_QUEUE_SIZE, we perform __queue_flush().
Since we have a
AMDGPU_INFO_NUM_HANDLES
and a new struct drm_amdgpu_info_num_handles to
get these values.
v2:
* Generated using make headers_install.
* Generated from linux-stable/master commit
a121103c922847ba5010819a3f250f1f7fc84ab8
Suggested-by: Emil Velikov <emil.l.veli...@gmail.com>
Signed-off-by: Arinda
From: Arindam Nath <arindam.n...@amd.com>
User might want to query the maximum number of UVD
instances supported by firmware. In addition to that,
if there are multiple applications using UVD handles
at the same time, he might also want to query the
currently used number of handles.
For t
From: Arindam Nath <arindam.n...@amd.com>
Change History
--
v3: changes suggested by Christian
- Add a check for UVD IP block using AMDGPU_HW_IP_UVD
query type.
- Add a check for asic_type to be less than
CHIP_POLARIS10 since starting Polaris, we support
unlimited UVD ins
