static array of pipe index to plane index map.
Populate the array properly and use in appropriate places.
Reviewed-by: Xi (Alex) Liu
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
Signed-off-by: Hersen Wu
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 45 ++--
.../amd/display
or space fields before
calling into DC to program DP test pattern.
Reviewed-by: Aurabindo Pillai
Acked-by: Hersen Wu
Signed-off-by: George Shen
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/
From: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Aric Cyr
Summary:
- Enable DCN35 physymclk root clock gating
- Fix DP automation test pattern bug
- Disable OTG for mode switch from TMDS to FRL
- Refactor DML2
- Revert Fix handling duplicate planes on one stream
- Revert Enable DCN clock
From: Daniel Miess
[Why]
Enable the last of the RCO options for dcn35
[How]
Breakout RCO from dccg35_set_physymclk so that
physymclk RCO can be set in dccg_init without
disabling physymclk
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
From: Joshua Aberback
[Why]
DCN32 uses ABM register definitions in dcn32_resource.h, remove
duplicate from dce_abm.h to avoid confusion.
Reviewed-by: Dillon Varone
Acked-by: Hersen Wu
Signed-off-by: Joshua Aberback
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
From: Ovidiu Bunea
[why]
Doing a mode timing change causes a hang when OTG is not disabled.
[how]
Add link_enc null check in disable_otg_wa to cover this case.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Ovidiu Bunea
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd
From: Chaitanya Dhere
Clean-up the code to remove references of all unused
dml architecture versions since only dml2 is actively
used.
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Chaitanya Dhere
Signed-off-by: Hersen Wu
---
.../amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 16
From: Sung Joon Kim
This reverts commit 2b30049e735fce887108ed4d01726c4daf69ed3d
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
Signed-off-by: Hersen Wu
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 45 ---
.../amd/display/dc/dml2/dml2_internal_types.h
ommit introduces a new
optc.h file and extracts the code from dcn10_optc to this new file.
Reviewed-by: Hamza Mahfooz
Acked-by: Hersen Wu
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 186 +--
dr
From: Wenjing Liu
[why]
There is a case when we are switching from ODM combine to Subvp where
minimal transition based off subvp state is required. In thise case, we
need to save and restore mall state when applying minimal transition.
Reviewed-by: Dillon Varone
Acked-by: Hersen Wu
Signed-off
From: Daniel Miess
[Why]
DCN clock gating enablement is preventing light up on
high resolution DSC display
[How]
This reverts commit 933b6692d58671e47dff15b77abe69ccb4891298.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc
From: Alvin Lee
[Description]
- Similar to FPO, SubVP should also force cursor P-State
allow instead of relying on natural assertion
- Implement code path to force and unforce cursor P-State
allow for SubVP
Reviewed-by: Samson Tam
Acked-by: Hersen Wu
Signed-off-by: Alvin Lee
---
.../drm
Title: DC Patches October 30, 2023
Start from:
9379d9fc18582c69862dc25fb770ae2e102f29d6
drm/amd/display: 3.2.258
Stopped at:
0a6aa88e926196036c7cf9edb70924b659461617
drm/amd/display: 3.2.259
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Enable DCN35
logic
Enable more IPS options
Fix FRL assertion on boot
Fix missing blendTF programming
Update DP HPO MSA with colorimetry from test request
Fix handling duplicate planes on one stream
Acked-by: Hersen Wu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1
From: Sung Joon Kim
[why]
To help isolate static screen and
video playback tests, we want to enable
an IPS option to allow IPS only on D3 cycle.
[how]
Add DISABLE_DYNAMIC and DISABLE_ALL
IPS disable flags for user control.
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
From: Dennis Chan
[Why]
Current Desync IRQ handler will have some potential do not hit the
desync error case. We change to check both desync error HPD and DPCD.
Signed-off-by: Dennis Chan
Acked-by: Hersen Wu
Reviewed-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dc_types.h
From: ChunTao Tso
[Why]
For Replay, if we receive HPD, it doesn’t need to reboot the display.
We don’t need to return anything exactly.
[How]
Return nothing just because we don’t need to reboot the display.
Signed-off-by: ChunTao Tso
Acked-by: Hersen Wu
Reviewed-by: Jerry Zuo
From: Daniel Miess
[Why & How]
Enable root clock optimization options for dcn35
for power savings
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
.../gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c| 1 +
.../drm/amd/display/dc/dcn35/dcn35_resour
From: Dennis Chan
[why]
It's useful to disable the recovery mechanism when debugging replay
desync errors.
Signed-off-by: Dennis Chan
Acked-by: Hersen Wu
Reviewed-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 3 ++-
.../drm/amd/display/dc/link/prot
From: Anthony Koo
- Increase number of bits for IPS boot option
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub
From: George Shen
[Why]
An SCR was made to the DP2.0 spec that updated the bit field definition
for UHBR13.5 in the test link rate DPCD register.
[How]
Add new translation to match the SCR update. Keep old translation for
backwards compatibility.
Reviewed-by: Wenjing Liu
Acked-by: Hersen Wu
From: Daniel Miess
[Why & How]
Enable dcn clock gating for dcn35
Disable DTBCLK gate before FRL link training
and re-enable afterwards
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
From: Fangzhi Zuo
Enable 12 and 16 max_slices for DP2 DSC
Reviewed-by: Alvin Lee
Acked-by: Hersen Wu
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 10 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 11 +++
drivers/gpu/drm/amd
d-by: Harry Wentland
Acked-by: Hersen Wu
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_transl
context instead.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Taimur Hassan
---
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35
From: Ilya Bakoulin
[Why]
When MPO surface pixel format is not ARGB, fast update can miss
programming blendTF.
[How]
Set the gamma_change update flag on blend_tf change.
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c
static array of pipe index to plane index map.
Populate the array properly and use in appropriate places.
Reviewed-by: Xi (Alex) Liu
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
---
.../display/dc/dml2/dml2_dc_resource_mgmt.c | 45 +++
.../amd/display/dc/dml2/dml2_internal_types.h
.
Reviewed-by: Wenjing Liu
Acked-by: Hersen Wu
Signed-off-by: George Shen
---
.../drm/amd/display/dc/link/accessories/link_dp_cts.c| 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
b/drivers/gpu/drm/amd
From: Yihan Zhu
[WHY & HOW]
Enabling SCE after boot up will cause color distortion.
Reviewed-by: Ovidiu Bunea
Acked-by: Hersen Wu
Signed-off-by: Yihan Zhu
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dri
From: Anthony Koo
- Minor formatting changes
- Update defines to match the bit width of the field it is used for
- Add new boot up bits to control HW sub block regions power
down
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub
From: Sung Joon Kim
[why]
Make sure to ungate the clocks on boot
so programming sequence is done successfully.
[how]
Move the ungate logic after bios init.
Reviewed-by: Xi (Alex) Liu
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/hwss/dcn35
Acked-by: Hersen Wu
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
b/drivers/gpu/drm/amd/displ
dereference of timing generator
Acked-by: Hersen Wu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e6e6377a8ce3..220609361eab 100644
From: Daniel Miess
[Why]
HDCP2 enablement fails when domain22 is set to force
power on
[How]
Disable force power on for domain22 on startup
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c | 10
From: Ilya Bakoulin
[Why]
Full update is not required on surface blend TF change.
[How]
Update full_update_required condition.
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
1 file changed, 1 deletion(-)
diff
From: "JinZe.Xu"
[Why]
On some systems dmub commands run at high IRQ, so long running
commands will block other interrupts.
[How]
Decouple wait_for_idle from dmcub queue/execute/wait.
Reviewed-by: Josip Pavic
Acked-by: Hersen Wu
Signed-off-by: JinZe.Xu
---
drivers/gpu/drm/amd/
From: Wayne Lin
[Why & How]
Check whether assigned timing generator is NULL or not before
accessing its funcs to prevent NULL dereference.
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++--
1 file change
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Enable HPD handler for replay.
* Add disable replay desync error check.
* Add more IPS options for static screen and video playback.
* Add test link rate UHBR13.5 for DP2.0.
* Enable 12 and 16 max_slices for DP2 DS
From: Sung Joon Kim
[why]
There are some registers for plane
color that are skipped programming
on resume. Need to add those as part
of the sequence.
[how]
Add new function hook for programming
plane color control.
Reviewed-by: Duncan Ma
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
: Hersen Wu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a46b8b47b756..073bf00c6fdc 100644
--- a/drivers/gpu
ate --> dm_resume
therefore, linux dc-pplib interface of navi10/12/14 is different
from that of Renoir.
Signed-off-by: Hersen Wu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++
1 file changed, 64 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_d
: Hersen Wu
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 +--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 22 +-
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 5 +++--
3 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config,
there is build error. struct dpm_clocks shoud not be
guarded.
Signed-off-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b
enable dc get dmp clock table and set dcn watermarks
via pplib.
Signed-off-by: Hersen Wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 93 +++
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h| 2 +-
2 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
there are two paths for renoir dc access smu.
one dc access smu directly using bios smc
interface: set disply, dprefclk, etc.
another goes through pplib for get dpm clock
table and set watermmark.
Signed-off-by: Hersen Wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 16 +---
drivers/gpu
[WHY] clock unit mis-match between caller DC and SMU interface.
dc pass lock in mhz. the same unit as smu. no covert is needed.
[HOW] remove covert_10k_to_mhz in smu interface
this fixes corruption issue with 4k @60 display and stutter
mode enable
Signed-off-by: hersen wu
[WHY] clock unit mis-match between caller DC and SMU interface.
dc pass lock in mhz. the same unit as smu. no covert is needed.
[HOW] remove covert_10k_to_mhz in smu interface
Signed-off-by: hersen wu
---
.../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 17 ++---
1 file
: hersen wu
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 4 ++
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 76 ++
.../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 45 -
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 36 +-
.../gpu
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