From: Martin Tsai
[Why]
On current design, driver cannot handle the interrupt for
down reply when link training is processing. The DOWN REQ
send before link training will keep in the pending DOWN REP
state in the queue.
It makes the next DOWN REQ be queued until time out.
[How]
To add a polling
From: Eric Yang
[why]
Previously we incorrectly skipped backlight control when stream is
present but dpms_off = true. This causes backlight to remain on in
the we boot up or resume into a external display only configuration
where VBIOS posted on the eDP.
[How]
Add dpms_off into the condition
From: David Francis
[Why]
amdgpu_dm_commit_planes was performing multi-plane
flips incorrectly:
It waited for vblank once per flipped plane
It prepared flip ISR and acquired the corresponding vblank ref
once per plane, although it closed ISR and put the ref once
per crtc
It called into dc
From: David Francis
[Why]
DC was assuming that any surface_update->scaling_info
meant the update was at least medium. However, if nothing
has changed there is no scaling to program, so there is
no problem with the update being fast
[How]
If every update flag is not set, the update is fast
From: Krunoslav Kovac
[Why] Our output TF calculation doesn't work if no user-specified gamma
correction. Normally, user provides this, but driver sohuld just assume
default (linear) gamma otherwise.
[How] Remove output TF dependency on user gamma being provided.
Signed-off-by: Krunoslav Kovac
From: Josip Pavic
[Why]
Current date based versioning doesn't tell us about feature version
and build version, and is not useful for debug.
[How]
Add versioning based on feature and build
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
From: David Francis
[Why]
We were assuming that any commit with allow_modeset == false
was a pageflip. This was against drm intention and only
worked by sheer luck
[How]
A pageflip is the change from one framebuffer to another
Signed-off-by: David Francis
Reviewed-by: Harry Wentland
From: Josip Pavic
[Why]
Need method of detecting which version of the DMCU FW is loaded and
load the appropriate iRAM.
[How]
Create definition for ABM 2.2 iRAM, and load it if the DMCU FW version
number matches the ABM 2.2 version; otherwise load ABM 2.1 iRAM.
Signed-off-by: Josip Pavic
From: David Francis
[Why]
Our old logic: if pageflip, update freesync and plane address.
Otherwise, update everything.
This over-updated on non-pageflip cases, and it failed to
update if pageflip and non-pageflip changes occurred on
the same commit
[How]
Update flip_addrs on pageflips.
Update
From: John Barberiz
[Why]
An uninitialized variable would randomly initialize to a large
value. This caused enough delay to fail DP Compliance Test 400.2.1.
[How]
Initialize the variable.
Signed-off-by: John Barberiz
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f362b04..8391bc3
From: Josip Pavic
[Why]
Improved contrast in ABM 2.2 is desired
[How]
Increase the contrast factor for ABM levels 2, 3 and 4
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 6 +++---
1 file changed, 3
From: Leo Li
Summary of change:
* Fixes for pageflipping logic
* Multiplane flipping support
* Make it more atomic
* Fix CRC capture on pipes with no active vblank reference
* Simplify commit for scaling and ABM changes
David Francis (5):
drm/amd/display: Simplify underscan and ABM
From: Eryk Brol
[Why]
Change DCN10 hubbub to use hubbub as a base and allow all future DCN
hubbubs to do the same instead of using DCN10_hubbub. This increases
readability and doesn't require future hubbubs to inherit anything
other than the base hubbub struct.
[How]
Create separate
From: David Francis
[Why]
Underscan and ABM are connector properties but require updates
to DC stream state. Previously, on updates to these properties
the affected stream and all its planes were committed.
This is unnecessary; only a few fields on the stream need
to be changed.
[How]
If
From: Eryk Brol
Virtual memory allows display to support flipping to surfaces which
are not allocated contiguously in memory with physical addresses,
instead a 1-4 level page table is used.
This is beneficial because it allows the scattering of large surfaces
to improve memory efficiency and
From: hersen wu
[Why] bios will light up eDP before sw driver loaded. sw driver will
check if eDP lighted up by bios by reading BIOS_SCRATCH_3. If yes,
sw driver will not power down eDP power, phy to save time.
definition of BIOS_SCRATCH_3 are missed for pre-raven asic. this
cuase eDP fast boot
From: Leo Li
This is a follow up to:
e28e1490794d ("drm/amd/display: Remove i2caux folder")
Some files were still left, so delete all of them.
CC: David Francis
CC: Harry Wentland
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 99
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Eric Bernstein
Check if VERT_FILTER_INIT_BOT and BLACK_OFFSET registers
exists in the DCN SCL IP block before trying to access.
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 42
From: Eric Yang
[Why]
On DCN1, there is an issue where on high BW config on single channel
systems, underflow will be observed if DCC is disabled. This issue
can be observed on several use cases. For this particular case,
it is observed when playing 4k video on 4k desktop with video downscaled
From: David Francis
[Why]
aux_payload should be the struct used inside dc to start
aux transactions. This will allow the old aux interface
to be seamlessly replaced.
[How]
Add three fields to aux_payload: reply, mot, defer_delay
This will mean that aux_payload has all data required
to submit a
From: David Francis
[Why]
The aux_engine struct is needlessly complex and
is defined multiple times. It contains function pointers
that each have only one version and are called only from
inside dce_aux.
[How]
Replace aux_engine with a new struct called dce_aux.
Remove all function pointers
From: Krunoslav Kovac
[Wjy] Some stress test is causing unexpected memory allocation
failure. This prevents null dereference but there will likely be problems
later, hard to gracefully handle memalloc fail for critical objects.
Signed-off-by: Krunoslav Kovac
Reviewed-by: Anthony Koo
Acked-by:
From: Josip Pavic
[Why]
When the DMCU's iRAM definition was moved to the newly created
power_helpers, a #pragma pack was lost, causing the iRAM to be misaligned
[How]
Restore the #pragma pack
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
From: David Francis
[Why]
The old aux interface goes through i2caux and the aux_engine
and engine function pointers. The multiple layers of indirection
make it hard to tell waht is happening. The aux algorithm
does not need to be this complicated: attempt to submit the
request. If you get an
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Leo Li
Summary of change:
* AUX interface cleanup and refactor
* Fix potential warning storm on Raven
* Fix vanishing cursor bug on Raven
Bayan Zabihiyan (1):
drm/amd/display: Add new infopacket definition
Charlene Liu (2):
drm/amd/display: fix PME notification not working in RV
From: Roman Li
[Why]
Hotplug on raven results in REG_WAIT_TIMEOUT warning
due to failing attempt to lock disabled otg for the hubp
interdependent pipes programming.
[How]
Don't setup pipe interdependencies for disabled otg.
Also removed the unnecessary duplicate logic checks.
Signed-off-by:
From: Bayan Zabihiyan
Modify freesync module to build VTEM infopackets when in HdmiVRR mode
Signed-off-by: Bayan Zabihiyan
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
.../drm/amd/display/modules/freesync/freesync.c| 94 --
From: Joshua Aberback
[Why]
The driver will crash on dce hardware due to a null function pointer.
[How]
- bring back "program_csc_matrix" functionality as "program_output_csc" for
dce110
- dce110 doesn't use the "opp_id" parameter, so use 0 when there's no hubp
Signed-off-by: Joshua Aberback
From: hersen wu
[WHY] clarify dal input parameters to pplib interface, remove
un-used parameters. dal knows exactly which parameters needed
and their effects at pplib and smu sides.
current dal sequence for dcn1_update_clock to pplib:
1.smu10_display_clock_voltage_request for dcefclk
From: Nicholas Kazlauskas
[Why]
The cursor vanishes when touching the top of edge of the screen for
Raven on Linux.
This occurs because the cursor height is not taken into account when
deciding to disable the cursor.
[How]
Factor in the cursor height into the cursor calculations - and mimic
From: Joshua Aberback
[Why]
In certain scenarios the ramp parameter come in as NULL, which crashes
because this function doesn't guard properly in the early return.
[How]
- parameter mapUserRamp should be the guard (false means no ramp)
- remove checking ramp in early return
Signed-off-by:
From: Martin Tsai
[why]
To resume system before entering S0i3 completely will cause PSP not
reload DMCU FW since there is not HW power state change.
In this case, driver cannot get correct DMCU version from IRAM
since driver override it and DMCU didn't reload to update it.
It makes driver return
From: abdoulaye berthe
[Why]
1-Test equipment does not reset test automation flag after completing
current test causing the next test to fail.
2.When test request is empty, we shouldn't ack the test.
[How]
1-Driver should always clear test equipment automation test request
when request is
From: Dmytro Laktyushkin
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 6 +++---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
From: Leo Li
This reverts commit 717276b9256f5d97b43e53adca1670cee2c45db2.
The reverted patch was a workaround that addressed an issue fixed by:
4364bcb2cd21 ("drm: Get ref on CRTC commit object when waiting for
flip_done")
Signed-off-by: Leo Li
Reviewed-by: Nicholas Kazlauskas
---
From: Charlene Liu
[Why]
PPLIB not receive the PME when unplug.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
From: Derek Lai
[Why]
If eDP ver >= 1.4,
the Source device must use LINK_RATE_SET.
[How]
Get LINK_RATE_SET by reading DPCD 10h-1fh,
then write DPCD 00115h before link training.
Signed-off-by: Derek Lai
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Tony Cheng
[why]
separate register access from logic to allow us abstract register sequences
[how]
consolidate mask and value first then apply to register.
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc_helper.c | 36
From: Leo Li
[Why]
To reduce indentation of dm_update_planes, and to make it operate on
single plane instances.
[How]
Move iteration of plane states into atomic_check.
No functional change is intended.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 220
From: Leo Li
[Why]
To reduce indent in dm_update_crtcs, and to make it operate on single
instances.
[How]
Move iteration of plane states into atomic_check.
No functional change is intended.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 341
From: Ken Chalmers
[Why]
32-bit builds break when doing 64-bit division directly.
[How]
Use the div_u64() function instead to perform the division.
Fixes:
https://lists.freedesktop.org/archives/dri-devel/2018-December/201008.html
Signed-off-by: Ken Chalmers
Reviewed-by: Leo Li
---
From: Leo Li
drm_atomic_helper_check_planes() calls the crtc atomic check helpers. In
an attempt to better align with the DRM framework, we can move the
entire dm_update dance to the crtc check helper (since it essentially
checks that we can align DC states to what DRM is requesting)
From: Leo Li
In preparation of implementing the CRTC atomic_check helper,
dm_update_crtcs need to operate on single instances.
Move iteration of plane states into atomic_check.
No functional change is intended.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 331
From: Leo Li
In preparation for moving the dm_update dance to the crtc atomic helper,
the lock_and_validation_needed flag need to be de-localized.
Move it to dm_*_states, and update it in the corresponding dm_update*
functions. Add a function to determine if DC global locking is needed by
From: David Francis
[Why]
The function dc_commit_updates_for_stream had a parameter called
plane_states. It was never used. It was getting in the way
of some cleanup work
[How]
Remove it
Signed-off-by: David Francis
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
From: Ken Chalmers
[Why]
Users would like more accurate pixel clocks, especially for fractional
"TV" frame rates like 59.94 Hz.
[How]
Store and communicate pixel clocks with 100 Hz accuracy from
dc_crtc_timing through to BIOS command table setpixelclock call.
Signed-off-by: Ken Chalmers
From: SivapiriyanKumarasamy
[WHY]
Currently, when the VSP infopacket is rebuilt in DM, it is not updated
when being programmed in encoder.
[HOW]
Add new VSP case for update_info_frame
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Acked-by: Krunoslav Kovac
Acked-by: Leo Li
From: Leo Li
[Why]
We'll need a way to differentiate Vega 20 in DC
[How]
Add a DCE_VERSION_12_1 enum, which will be returned as the DC version if
the ASIC used is a Vega 20.
Signed-off-by: Leo Li
Reviewed-by: David Francis
---
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 1
From: Yongqiang Sun
[Why]
passive update planes still spends a litte more
time on some cases.
[How]
Remove unnecessary trace which involving in some register read.
Disable debug output for release build.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Leo Li
[Why]
context->bw.dce.dispclk_khz is being cached into unpatched_clock, then
restored at end of function call. This is needlessly complex
[How]
Instead, use a local patched_clock variable. Leave
context->bw.dce.dispclk_khz alone.
No functional change is intended.
Signed-off-by:
From: Leo Li
[Why]
When XGMI is enabled, the DP reference clock needs to be adjusted
according to the XGMI spread spectrum percentage and mode. But first,
we need the ability to fetch this info.
[How]
Within the BIOS parser, Read from vBIOS when XGMI SS info is requested.
In addition, diags
From: Dmytro Laktyushkin
This is a dual channel format and should be treated like other
video formats
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Leo Li
[Why]
When XGMI is enabled, we need to adjust the dprefclk according to the
WAFL link's spread spectrum info. This is for VG20 (DCE121) only.
[How]
dce_clk_mgr already stores SS info, currently being used by audio clock.
Therefore, patch the clk_mgr's SS info with the xGMI SS info,
From: Fatemeh Darbehani
[Why]
PPLib has impelemented the new pp_smu interface
[How]
Use the new functions if available instead of the old interface
'set_display_requirement' and 'dcn1_pplib_apply_display_requirements'.
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Fatemeh Darbehani
Acked-by:
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Wenjing Liu
[why]
DP LL CTS1.4 4.3.2.1 test failure.
[how]
The failure is caused by not handling DP link loss
hpd short pusle during set mode. The change is to read link status
before set mode link training. If link is lost, re-verify link caps.
Signed-off-by: Wenjing Liu
Reviewed-by:
From: Ken Chalmers
[Why]
For more informative debugging.
[How]
Add timing generator and PLL ids to output, to make it clear which pixel
clock is being set.
Signed-off-by: Ken Chalmers
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 8
From: Dmytro Laktyushkin
This will allow us to program dscclk to required value
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 7
From: Leo Li
[Why]
This fixes an regression introduced by:
drm/amd/display: add stream ID and otg instance in dc_stream_state
During driver initialization, a null pointer deref is raised. This is
caused by searching for a stream status in the dc->current_state before
the dc_state swap
From: Wenjing Liu
[why]
Some dongle doesn't have a valid extended dongle caps,
but we still set the extended dongle caps to be valid.
This causes validation fails for all timing.
[how]
If no dp_hdmi_max_pixel_clk is provided,
don't use extended dongle caps.
Signed-off-by: Wenjing Liu
From: Paul Hsieh
[WHY]
On customer board, there is one pluse (1v , < 1ms) on
DDC_CLK pin when plug / unplug DP cable. Driver will read
it and config DP to HDMI/DVI dongle.
[HOW]
If there is a real dongle, DDC_CLK should be always pull high.
Try to read again to recovery this special case. Retry
From: Eric Bernstein
[Why]
There are different reasons for Validation failure error during
atomic_check
[How]
Add better logging of the reason for validation failure
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
From: Harry Wentland
[Why]
In certain configurations, such as PX configs or some Vega20 parts
DC gets created without connectors.
[How]
Drop the dm_error print when no connectors.
Signed-off-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
Acked-by: Leo Li
---
From: Imad Syed
They're not being used, so remove them.
Signed-off-by: Imad Syed
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
From: SivapiriyanKumarasamy
[WHY]
There is an extra null check for fs_params in the
build_freesync_hdr function detected by Smatch.
[HOW]
1) Remove the extra null check since it is checked in the
caller.
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
From: David Francis
[Why]
DC warns when a REG_WAIT takes a while and full-on errors
with stack dump on REG_WAIT timeout. Most of the time it isn't
a real issue.
[How]
Make DC cool its jets - taking a while is a debug message (because
it is not something that normal users should need to be
From: Fatemeh Darbehani
[Why]
To make sure future changes in DAL for SMU msgs will not change the current
behaviour
and to make sure clock registeres are programmed correctly based on SMU msgs
that DAL sends.
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
From: Leo Li
[Why]
It's not being used anywhere.
[How]
Remove it.
Signed-off-by: Leo Li
Reviewed-by: David Francis
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
From: Eric Yang
[Why]
Skipping initial link training will result in no verified link cap for
mode enumeration. Some versions of the BIOS seem to have PHY programming
sequence issue as well if initial link training is skipped, resulting in
a softlock in BIOS command table.
[How]
Identify the
From: Wenjing Liu
[why]
Some components depend on dc to constuct
but need to assign callback functions to dc.
[how]
Instead of assigning dc callback functions in dc_create,
decouple the callback init to a standlone function after dc_create. This
is currently a no-op.
Signed-off-by: Wenjing Liu
From: Jun Lei
[why]
dc_stream_state containing a pointer to sink is poor design.
Sink describes the display, and the specifications or capabilities
it has. That information is irrelevant for dc_stream_state, which describes
hardware state, and is generally used for hardware programming. It
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Yongqiang Sun
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: David Francis
[Why]
Backlight is conceptually a property of links, not streams.
All backlight programming is done on links, but there is a
stream property bl_pwm_level that is used to restore backlight
on dpms on and s3 resume. This is unnecessary, as backlight
is already restored by
From: Hugo Hu
[Why]
So that we can adjust fclk for debugging purposes.
[How]
Add option to force adjust fclk request to pplib.
Signed-off-by: Hugo Hu
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
From: Eric Yang
[Why]
YCbCr420 packing format uses two chanels for luma, and 1
channel for both chroma component. Our previous implementation
did not account for this and results in every other pixel having
very high luma value, showing greyish color instead of black.
YCbCr444 = ; .
From: Roman Li
[Why]
The visual corruption due to low display clock value observed on some
systems
[How]
There was earlier patch for dspclk:
'drm/amd/display: Raise dispclk value for dce_update_clocks'
Adding +15% workaround also to to dce112_update_clocks
Signed-off-by: Roman Li
Reviewed-by:
From: Krunoslav Kovac
[Why]
We are not correctly handling the wrap around case.
VLine interrupt is relative to position of VUpdate interrupt.
Both VUpdate interrupt and VLine interrupt could possibly
be in front porch or back porch.
[How]
Fix wraparound case by checking for line number that is
From: Dmytro Laktyushkin
DV have made updates to DCN dml which we need to pull in
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 7 --
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
From: David Francis
[Why]
ABM enablement testing can be automated if a way of reading
target and current hardware backlight is available
[How]
Expand debugfs interface with two new entries.
Hook directly into dc interface. Units are as
a fraction of 0x1000 = 100%
Use the built-in amdgpu
From: Dale Zhao
[Why]
In 99% user case, edp will be post by vbios.
In 1% / current case: Lenovo don't light up edp panel in vbios
post stage, vbios won't be lit up. Thus in dal when we init DCN
10 hw, we power up edp, then we start detect_sink, but internal
time is too short, when we detect
From: Lewis Huang
[Why]
Driver didn't check plane size and surface size is mismatch.
It will cause pitch data incorrect.
[How]
Add condition to check is plane change and update surface
Signed-off-by: Lewis Huang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Eric Yang
[why]
There was a recent fix in the BW spreadsheet to allow timing with very
large vblank. Need to be ported into driver.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c |
From: Dmytro Laktyushkin
An earlier change added update of interdependent dlg/ttu params for pipes
not being updated in the current call. The code fails to check if the other
pipes are actually active yet causing an assert.
This change adds a check for surface presence on the pipes before
From: Eric Bernstein
Expose this function for future use.
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 2 ++
2 files
From: Jun Lei
[why]
stream ID allows DMs to avoid memory address comparisons to compare
stream equality.
otg_instance allows DC to more rigorously define when otg_instance
can change. specifically, it is now defined to be only mutable when
dc_stream_state
changes. This is better than a "get
From: Jun Lei
Signed-off-by: Jun Lei
Reviewed-by: Nevenko Stupar
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
From: Dmytro Laktyushkin
Remove braces around single-line conditionals
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Leo Li
Acked-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++
1 file changed, 2 insertions(+), 4
From: Steven Chiu
Signed-off-by: Steven Chiu
Reviewed-by: Shahin Khayyer
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Leo Li
Lots of patches this time around, my appologies :) I've been falling
behind on preparing these, so doing some catch-up here.
Summary of change:
* Fix display corruption on some systems running Polaris
* Remove/demote some error messages to warnings
* Architectural refactors and
From: Eric Bernstein
1) Rename and make public definition of input CSC matrix struct.
2) Make wm_read_state() function an interface of hubbub, and check
if watermark registers exist before read/write to them.
3) Check if OTG_INTERLACE_CONTROL register exists before updating
4) Add dummy
From: Leo Li
In particular, we need the mmMC_VM_XGMI_LFB_CNTL register, for
determining if xGMI is enabled on VG20. This will be used by DC to
determine the correct spread spectrum adjustment for display and audio
clocks.
Signed-off-by: Leo Li
Reviewed-by: Alex Deucher
---
From: David Francis
dce100 was set to always pass safe_to_lower = false
to the clock manager
Thus, on suspend the clocks were not being set to 0
which is incorrect behaviour
This was causing s3 resume to blackscreen on intel
CPUs with dce100 GPUs attached
(Note that the hash in this Fixes:
From: SivapiriyanKumarasamy
Dithering needs to be enabled or disabled as requested. If
dc_stream_update->dither_option is non-null, program the FMT blocks.
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Reviewed-by: Krunoslav Kovac
Acked-by: Leo Li
---
From: Fatemeh Darbehani
[Why]
To prepare for clock debug logging. With the exception of removing
max_supported_dppclk_khz from logs, there are no functional changes.
[How]
Add clk_bypass struct and clean up buffer logic
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Yongqiang Sun
Acked-by: Su
From: hersen wu
[WHY] fbc is within the data path from memory to dce. while
re-configure mc dmif, fbc should be enabled. otherwise, fbc
may not be enabled properly.
[HOW] before re-configure mc dmif, disable fbc, only after
dmif re-configuration fully done, enable fbc again.
From: Leo Li
Summary of change:
* Initial documentation of DC
* Implement tracing in DC
* Fix AUX transaction race
Chiawen Huang (1):
drm/amd/display: Add customizable tracing event
David Francis (3):
drm/amd/display: Start documentation of DC
drm/amd/display: Add tracing to dc
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