On Thu, Jun 11, 2020 at 7:58 AM Tom St Denis wrote:
>
> Even though they are technically MMIO registers I put the bits with the sqind
> block
> for organizational purposes.
>
> Requested for UMR debugging.
>
> Signed-off-by: Tom St Denis
Reviewed-by: Alex Deucher
> ---
>
Even though they are technically MMIO registers I put the bits with the sqind
block
for organizational purposes.
Requested for UMR debugging.
Signed-off-by: Tom St Denis
---
.../include/asic_reg/gc/gc_10_1_0_offset.h| 3 ++-
.../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 16
