Re: [PATCH] drm/amd/display: Add irq register entry for dmub

2021-03-17 Thread Harry Wentland
On 2021-03-17 12:21 p.m., Rodrigo Siqueira wrote: DCN2.1 and DCN3.0 are missing some macros that register irq entries which cause compilation errors. This commit introduces those macros and fix the compilation error. Cc: Wayne Lin Cc: Solomon Chiu Fixes: 53e9c0f651421136 ("drm/amd/display:

Re: [PATCH] drm/amd/display: Add irq register entry for dmub

2021-03-17 Thread Deucher, Alexander
: [PATCH] drm/amd/display: Add irq register entry for dmub DCN2.1 and DCN3.0 are missing some macros that register irq entries which cause compilation errors. This commit introduces those macros and fix the compilation error. Cc: Wayne Lin Cc: Solomon Chiu Fixes: 53e9c0f651421136 ("drm/amd/di

[PATCH] drm/amd/display: Add irq register entry for dmub

2021-03-17 Thread Rodrigo Siqueira
DCN2.1 and DCN3.0 are missing some macros that register irq entries which cause compilation errors. This commit introduces those macros and fix the compilation error. Cc: Wayne Lin Cc: Solomon Chiu Fixes: 53e9c0f651421136 ("drm/amd/display: Support vertical interrupt 0 for all dcn ASIC")