> Sent: Monday, June 8, 2020 2:00 PM
> To: Alex Deucher ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: RE: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on
> renoir (v2)
>
> According to reg_offset assignment in amdgpu_discovery_reg_base_init() the
>
ike
> -Original Message-
> From: Alex Deucher
> Sent: Friday, June 5, 2020 11:40 PM
> To: amd-gfx@lists.freedesktop.org; Liang, Prike
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir
> (v2)
>
> The PWR blo
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, June 5, 2020 11:40 PM
To: amd-gfx@lists.freedesktop.org; Liang, Prike
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/soc15: fix using
The PWR block moved into SMUIO, so the ip discovery table
doesn't have an entry for PWR, but the register has the
same absolute offset, so just patch up the offsets after
updating the offsets from the IP discovery table.
v2: PWR became SMUIO block 1. fix the mapping.
Signed-off-by: Alex Deucher
