: [PATCH] drm/amdgpu: Fix incorrect register offsets for Sienna
Cichlid
[AMD Official Use Only]
checks should be adev->asic_type >= CHIP_SIENNA_CICHLID so we cover other
gfx10.3 asics as well. With that fixed:
Reviewed-by: Alex Deucher
mailto:alexander.deuc...@a
op.org ; Deucher,
Alexander ; Zhang, Hawking ;
Deng, Emily ; Liu, Monk ; Zhou, Peng Ju
; Chen, Horace
Cc: Ming, Davis ; Khaire, Rohit ;
Koenig, Christian ; Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have dif
RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
