On 2021-11-09 2:12 p.m., Ramesh Errabolu wrote:
MMIO/DOORBELL BOs encode control data and should be pinned in GTT
domain before enabling PCIe connected peer devices in accessing it
Signed-off-by: Ramesh Errabolu
Reviewed-by: Felix Kuehling
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.
alone patch for the DKMS branch as well.
Thanks for pointing this out.
Regards,
Ramesh
From: Errabolu, Ramesh
Sent: Tuesday, November 9, 2021 1:32 AM
To: Yu, Lang
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain
I will experiment to
MMIO/DOORBELL BOs encode control data and should be pinned in GTT
domain before enabling PCIe connected peer devices in accessing it
Signed-off-by: Ramesh Errabolu
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 70 +++
1 file changed, 70 insertions(+)
diff --git a/drivers/g
rabolu, Ramesh
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain
>
> On Mon, Nov 08, 2021 at 07:37:44PM -0600, Ramesh Errabolu wrote:
> > MMIO/DOORBELL BOs encode control data and should be pinned in GTT
> > domain b
> Subject: Re: [PATCH] drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain
>
> On Mon, Nov 08, 2021 at 07:37:44PM -0600, Ramesh Errabolu wrote:
> > MMIO/DOORBELL BOs encode control data and should be pinned in GTT
> > domain before enabling PCIe connected peer devices in
[AMD Official Use Only]
Responses in line
-Original Message-
From: Yu, Lang
Sent: Monday, November 8, 2021 11:27 PM
To: Errabolu, Ramesh
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain
On Mon, Nov 08, 2021 at 07:37:44PM
On Mon, Nov 08, 2021 at 07:37:44PM -0600, Ramesh Errabolu wrote:
> MMIO/DOORBELL BOs encode control data and should be pinned in GTT
> domain before enabling PCIe connected peer devices in accessing it
>
> Signed-off-by: Ramesh Errabolu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 25
[AMD Official Use Only]
Responses in line
Regards,
Ramesh
-Original Message-
From: Kuehling, Felix
Sent: Monday, November 8, 2021 10:51 PM
To: amd-gfx@lists.freedesktop.org; Errabolu, Ramesh
Subject: Re: [PATCH] drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain
Am 2021-11-08 um
Am 2021-11-08 um 8:37 p.m. schrieb Ramesh Errabolu:
> MMIO/DOORBELL BOs encode control data and should be pinned in GTT
> domain before enabling PCIe connected peer devices in accessing it
The PCIe connected peer device access isn't an issue on the upstream
branch (yet). But in general, it is a go
MMIO/DOORBELL BOs encode control data and should be pinned in GTT
domain before enabling PCIe connected peer devices in accessing it
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 25 +
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 55 +++
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