Am 2020-04-20 um 3:42 a.m. schrieb Tao, Yintian:
> Hi Felix
>
> I have one question about function kgd_gfx_v9_hiq_mqd_load(). I see it
> directly write contents into kiq ring and not wait for the fence. Do you know
> how KFD know the hiq_mqd_load complete? Thanks in advance.
That's probably a b
ther read
operation.
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Liu, Monk
Sent: Monday, April 20, 2020 5:28 AM
To: Koenig, Christian ; Kuehling, Felix
; Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: refine kiq read register
4:48 PM
To: Liu, Monk ; Koenig, Christian ; Kuehling,
Felix ; Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
Hi Monk,
yeah, that is certainly problematic. But we have some maximum size for the KIQ
submission, don't we?
The only alt
oenig, Christian ;
Kuehling, Felix ; Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
Hi Monk,
yeah, that is certainly problematic. But we have some maximum size for the KIQ
submission, don't we?
The only alternative would be to do
not
overwrite job 2.
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Koenig, Christian
Sent: Monday, April 20, 2020 4:26 PM
To: Liu, Monk ; Kuehling, Felix ; Tao,
Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq r
___
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Koenig, Christian
Sent: Monday, April 20, 2020 4:26 PM
To: Liu, Monk ; Kuehling, Felix ;
Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
That is actually only a
27;s finished
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Christian König
Sent: Monday, April 20, 2020 4:17 PM
To: Liu, Monk ; Koenig, Christian ; Kuehling,
Felix ; Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq
2020 4:17 PM
To: Liu, Monk ; Koenig, Christian ;
Kuehling, Felix ; Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
> Yintian's patch has nothing to do with the result you mentioned the
> command being overwritten by new in
an
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: refine kiq read register
Previously we ended up with an invalid value in a concurrent register read, now
the KIQs overwrites its own commands and most likely causes a hang or the
hardware to execute something random.
Yintian's patch ha
ent: 2020年4月20日 15:19
To: Liu, Monk ; Kuehling, Felix ;
Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
Hi Monk,
> Can we first get the first problem done ?
Please absolutely not! See the problem introduced here is quite worse than th
Kuehling, Felix
; Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: refine kiq read register
>>> Previously we ended up with an invalid value in a concurrent register read,
>>> now the KIQs overwrites its own commands and most likely causes a hang
To: Liu, Monk ; Kuehling, Felix ;
Tao, Yintian
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
Hi Monk,
> Can we first get the first problem done ?
Please absolutely not! See the problem introduced here is quite worse than the
actual fix.
Previousl
ay, April 20, 2020 1:03 AM
To: Kuehling, Felix ; Tao, Yintian ;
Liu, Monk
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
Am 17.04.20 um 17:39 schrieb Felix Kuehling:
Am 2020-04-17 um 2:53 a.m. schrieb Yintian Tao:
According to the current kiq r
alization Team |AMD
-Original Message-
From: Christian König
Sent: Monday, April 20, 2020 1:03 AM
To: Kuehling, Felix ; Tao, Yintian
; Liu, Monk
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
Am 17.04.20 um 17:39 schrieb Felix Kuehling:
>
: refine kiq read register
Am 2020-04-17 um 2:53 a.m. schrieb Yintian Tao:
> According to the current kiq read register method, there will be race
> condition when using KIQ to read register if multiple clients want to
> read at same time just like the expample below:
> 1. client-A s
Am 17.04.20 um 17:39 schrieb Felix Kuehling:
Am 2020-04-17 um 2:53 a.m. schrieb Yintian Tao:
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A sta
Am 2020-04-17 um 2:53 a.m. schrieb Yintian Tao:
> According to the current kiq read register method,
> there will be race condition when using KIQ to read
> register if multiple clients want to read at same time
> just like the expample below:
> 1. client-A start to read REG-0 throguh KIQ
> 2. clie
,
Alexander ; Zhang, Hawking ;
Ming, Davis ; Jiang, Jerry (SW)
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: refine kiq read register
Hi Christian
mmRLC_SPM_MC_CNTL
this register is a RLC register, with my understanding it is PF&VF share
register, and I did experiment pr
; Deucher, Alexander ;
Zhang, Hawking
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
> Dynamic alloc each time doing KIQ reg read is a overkill to me
Yeah, that is a rather good argument.
> Now we do KIQ read and write *every time* we d
___
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Koenig, Christian
Sent: Friday, April 17, 2020 4:59 PM
To: Liu, Monk ; Tao, Yintian ; Kuehling, Felix
; Deucher, Alexander ; Zhang, Hawking
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm
her, Alexander ;
Zhang, Hawking
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq read register
Looks like a rather important bug fix to me, but I'm not sure if writing the
value into the ring buffer is a good idea.
See we wanted to map the ring buffers read only a
Tao
Sent: Friday, April 17, 2020 2:53 PM
To: Liu, Monk
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: [PATCH] drm/amdgpu: refine kiq read register
According to the current kiq read register method, there will be race condition
when using KIQ to read register if multiple clients want to re
this way
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Yintian Tao
Sent: Friday, April 17, 2020 2:53 PM
To: Liu, Monk
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: [PATCH] drm/amdgpu: refine kiq read register
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 throug
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 throug
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