From: Chris Park <chris.p...@amd.com>
[Why]
I2C register name starts with 1, unlike other
registers that start with 0. This creates
a problem with the new register macro
refactoring when I2C HW objects are created
in an array.
[How]
Correct I2C register offset by making a new
macro to account for array offset.
Reviewed-by: Charlene Liu <charlene....@amd.com>
Acked-by: Pavle Kotarac <pavle.kota...@amd.com>
Signed-off-by: Chris Park <chris.p...@amd.com>
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 9 ++++++++-
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 17 +++++++++--------
.../drm/amd/display/dc/dcn321/dcn321_resource.c | 9 ++++++++-
3 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index ef0a6d468a10..5a21cf041732 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -152,6 +152,13 @@ enum dcn32_clk_src_array_id {
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ##
_BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
+#define SR_ARR_I2C(reg_name, id) \
+ REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) +
reg##reg_name
+
+#define SRI_ARR_I2C(reg_name, block, id)\
+ REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ##
_BASE_IDX) + \
+ reg ## block ## id ## _ ## reg_name
+
#define SRI_ARR_ALPHABET(reg_name, block, index, id)\
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name
## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
@@ -792,7 +799,7 @@ static struct dce_aux *dcn32_aux_engine_create(
#define i2c_inst_regs_init(id)\
I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
-static struct dce_i2c_registers i2c_hw_regs[6];
+static struct dce_i2c_registers i2c_hw_regs[5];
static const struct dce_i2c_shift i2c_shifts = {
I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index 60d8fad16eee..dbcdf8607ee9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -1175,18 +1175,19 @@ void dcn32_determine_det_override(struct dc_state
*context, display_e2e_pipe_par
#define I2C_HW_ENGINE_COMMON_REG_LIST_RI(id)
\
( \
- SRI_ARR(SETUP, DC_I2C_DDC, id), SRI_ARR(SPEED, DC_I2C_DDC, id),
\
- SRI_ARR(HW_STATUS, DC_I2C_DDC, id), SR_ARR(DC_I2C_ARBITRATION, id),
\
- SR_ARR(DC_I2C_CONTROL, id), SR_ARR(DC_I2C_SW_STATUS, id),
\
- SR_ARR(DC_I2C_TRANSACTION0, id), SR_ARR(DC_I2C_TRANSACTION1, id),
\
- SR_ARR(DC_I2C_TRANSACTION2, id), SR_ARR(DC_I2C_TRANSACTION3, id),
\
- SR_ARR(DC_I2C_DATA, id), SR_ARR(MICROSECOND_TIME_BASE_DIV, id)
\
+ SRI_ARR_I2C(SETUP, DC_I2C_DDC, id), SRI_ARR_I2C(SPEED, DC_I2C_DDC, id),
\
+ SRI_ARR_I2C(HW_STATUS, DC_I2C_DDC, id),
\
+ SR_ARR_I2C(DC_I2C_ARBITRATION, id),
\
+ SR_ARR_I2C(DC_I2C_CONTROL, id), SR_ARR_I2C(DC_I2C_SW_STATUS, id),
\
+ SR_ARR_I2C(DC_I2C_TRANSACTION0, id), SR_ARR_I2C(DC_I2C_TRANSACTION1,
id),\
+ SR_ARR_I2C(DC_I2C_TRANSACTION2, id), SR_ARR_I2C(DC_I2C_TRANSACTION3,
id),\
+ SR_ARR_I2C(DC_I2C_DATA, id), SR_ARR_I2C(MICROSECOND_TIME_BASE_DIV, id)
\
)
#define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
\
( \
- I2C_HW_ENGINE_COMMON_REG_LIST_RI(id), SR_ARR(DIO_MEM_PWR_CTRL, id),
\
- SR_ARR(DIO_MEM_PWR_STATUS, id)
\
+ I2C_HW_ENGINE_COMMON_REG_LIST_RI(id), SR_ARR_I2C(DIO_MEM_PWR_CTRL, id),
\
+ SR_ARR_I2C(DIO_MEM_PWR_STATUS, id)
\
)
#endif /* _DCN32_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index a93dc00ebfb5..8a89c28add0d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -159,6 +159,13 @@ enum dcn321_clk_src_array_id {
REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ##
_BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
+#define SR_ARR_I2C(reg_name, id) \
+ REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) +
reg##reg_name
+
+#define SRI_ARR_I2C(reg_name, block, id)\
+ REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ##
_BASE_IDX) + \
+ reg ## block ## id ## _ ## reg_name
+
#define SRI_ARR_ALPHABET(reg_name, block, index, id)\
REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name
## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
@@ -796,7 +803,7 @@ static struct dce_aux *dcn321_aux_engine_create(
#define i2c_inst_regs_init(id)\
I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
-static struct dce_i2c_registers i2c_hw_regs[6];
+static struct dce_i2c_registers i2c_hw_regs[5];
static const struct dce_i2c_shift i2c_shifts = {
I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
--
2.34.1
