[PATCH 034/102] drm/amdgpu: skip all gfx ring settings for Arcturus

[Alex Deucher]

From: Le Ma <le...@amd.com>

Signed-off-by: Le Ma <le...@amd.com>
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 +++++++++++++++++----------
 1 file changed, 25 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 0676ae38ec1e..3ac3ee7fcb1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3338,18 +3338,22 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device 
*adev)
        if (r)
                return r;
 
-       r = gfx_v9_0_cp_gfx_resume(adev);
-       if (r)
-               return r;
+       if (adev->asic_type != CHIP_ARCTURUS) {
+               r = gfx_v9_0_cp_gfx_resume(adev);
+               if (r)
+                       return r;
+       }
 
        r = gfx_v9_0_kcq_resume(adev);
        if (r)
                return r;
 
-       ring = &adev->gfx.gfx_ring[0];
-       r = amdgpu_ring_test_helper(ring);
-       if (r)
-               return r;
+       if (adev->asic_type != CHIP_ARCTURUS) {
+               ring = &adev->gfx.gfx_ring[0];
+               r = amdgpu_ring_test_helper(ring);
+               if (r)
+                       return r;
+       }
 
        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                ring = &adev->gfx.compute_ring[i];
@@ -3363,7 +3367,8 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
 
 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
 {
-       gfx_v9_0_cp_gfx_enable(adev, enable);
+       if (adev->asic_type != CHIP_ARCTURUS)
+               gfx_v9_0_cp_gfx_enable(adev, enable);
        gfx_v9_0_cp_compute_enable(adev, enable);
 }
 
@@ -3388,9 +3393,11 @@ static int gfx_v9_0_hw_init(void *handle)
        if (r)
                return r;
 
-       r = gfx_v9_0_ngg_en(adev);
-       if (r)
-               return r;
+       if (adev->asic_type != CHIP_ARCTURUS) {
+               r = gfx_v9_0_ngg_en(adev);
+               if (r)
+                       return r;
+       }
 
        return r;
 }
@@ -3538,8 +3545,9 @@ static int gfx_v9_0_soft_reset(void *handle)
                /* stop the rlc */
                adev->gfx.rlc.funcs->stop(adev);
 
-               /* Disable GFX parsing/prefetching */
-               gfx_v9_0_cp_gfx_enable(adev, false);
+               if (adev->asic_type != CHIP_ARCTURUS)
+                       /* Disable GFX parsing/prefetching */
+                       gfx_v9_0_cp_gfx_enable(adev, false);
 
                /* Disable MEC parsing/prefetching */
                gfx_v9_0_cp_compute_enable(adev, false);
@@ -3882,7 +3890,10 @@ static int gfx_v9_0_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
+       if (adev->asic_type == CHIP_ARCTURUS)
+               adev->gfx.num_gfx_rings = 0;
+       else
+               adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
        adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
        gfx_v9_0_set_ring_funcs(adev);
        gfx_v9_0_set_irq_funcs(adev);
-- 
2.20.1

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