From: Likun Gao <likun....@amd.com>
Add vega20_populate_umd_state_clk function to set pstate_sclk and pstate_mclk.
Signed-off-by: Likun Gao <likun....@amd.com>
Reviewed-by: Huang Rui <ray.hu...@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 27 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 3 +++
4 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e03132c..f5ffc9b 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -393,6 +393,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_populate_umd_state_clk(smu);
+ if (ret)
+ return ret;
+
/*
* Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
*/
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 24babb8..94013c5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -198,6 +198,9 @@ struct smu_context
struct smu_dpm_context smu_dpm;
struct smu_power_context smu_power;
struct smu_feature smu_feature;
+
+ uint32_t pstate_sclk;
+ uint32_t pstate_mclk;
};
struct pptable_funcs {
@@ -209,6 +212,7 @@ struct pptable_funcs {
int (*run_afll_btc)(struct smu_context *smu);
int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t
*feature_mask, uint32_t num);
int (*set_default_dpm_table)(struct smu_context *smu);
+ int (*populate_umd_state_clk)(struct smu_context *smu);
};
struct smu_funcs
@@ -316,6 +320,8 @@ struct smu_funcs
((smu)->ppt_funcs->append_powerplay_table ?
(smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
#define smu_set_default_dpm_table(smu) \
((smu)->ppt_funcs->set_default_dpm_table ?
(smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
+#define smu_populate_umd_state_clk(smu) \
+ ((smu)->ppt_funcs->populate_umd_state_clk ?
(smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index?
(smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index bca4085..d794290 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -526,6 +526,32 @@ static int vega20_set_default_dpm_table(struct smu_context
*smu)
return 0;
}
+static int vega20_populate_umd_state_clk(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+ struct vega20_single_dpm_table *gfx_table = NULL;
+ struct vega20_single_dpm_table *mem_table = NULL;
+
+ dpm_table = smu_dpm->dpm_context;
+ gfx_table = &(dpm_table->gfx_table);
+ mem_table = &(dpm_table->mem_table);
+
+ smu->pstate_sclk = gfx_table->dpm_levels[0].value;
+ smu->pstate_mclk = mem_table->dpm_levels[0].value;
+
+ if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
+ mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
+ smu->pstate_sclk =
gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
+ smu->pstate_mclk =
mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
+ }
+
+ smu->pstate_sclk = smu->pstate_sclk * 100;
+ smu->pstate_mclk = smu->pstate_mclk * 100;
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -535,6 +561,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.run_afll_btc = vega20_run_btc_afll,
.get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
.set_default_dpm_table = vega20_set_default_dpm_table,
+ .populate_umd_state_clk = vega20_populate_umd_state_clk,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
index 27b2f1e..ceba4f7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -23,6 +23,9 @@
#ifndef __VEGA20_PPT_H__
#define __VEGA20_PPT_H__
+#define VEGA20_UMD_PSTATE_GFXCLK_LEVEL 0x3
+#define VEGA20_UMD_PSTATE_MCLK_LEVEL 0x2
+
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
--
2.7.4
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