[PATCH 08/35] drm/amd/display: Update DCN31 for DCN35 support

[Alex Deucher]

From: Qingqing Zhuo <qingqing.z...@amd.com>

[Why & How]
Update DCN31 files for DCN35 usage.

Signed-off-by: Qingqing Zhuo <qingqing.z...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 .../amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h   | 10 ++++++++--
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c      |  6 ++++++
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h      |  3 +++
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
index e324e9b83136..51f5781325e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
@@ -104,7 +104,10 @@ struct dcn31_hpo_dp_link_encoder_registers {
        uint32_t RDPCSTX_PHY_CNTL6[5];
 };
 
-#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+       SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
        SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 
mask_sh),\
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
@@ -126,11 +129,14 @@ struct dcn31_hpo_dp_link_encoder_registers {
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE, TP_SQ_PULSE_WIDTH, 
mask_sh),\
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, 
mask_sh),\
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
-       SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, 
mask_sh),\
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, 
mask_sh),\
        SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
 
+#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+       DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh),\
+       DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+
 #define DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(type) \
        type DP_LINK_ENC_CLOCK_EN;\
        type DPHY_RESET;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
index 39a57bcd7866..8394e8c06919 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
@@ -62,6 +62,12 @@ static void hubp31_program_extended_blank(struct hubp *hubp,
        REG_UPDATE(BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, 
min_dst_y_next_start_optimized);
 }
 
+void hubp31_program_extended_blank_value(
+       struct hubp *hubp, unsigned int min_dst_y_next_start_optimized)
+{
+       hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized);
+}
+
 static struct hubp_funcs dcn31_hubp_funcs = {
        .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
        .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h
index c31a7b8f81ee..d688db79b750 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h
@@ -243,4 +243,7 @@ void hubp31_soft_reset(struct hubp *hubp, bool reset);
 
 void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);
 
+void hubp31_program_extended_blank_value(
+       struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);
+
 #endif /* __DC_HUBP_DCN31_H__ */
-- 
2.41.0