[Why]
We need to be able to specify slice width for DSC on aconnector
[How]
Getting slice width parameter from debugfs entry, if it is
a valid the value is set in connector's dsc preffered settings
structure. Which then overwrites dsc_cfg structure's parameters
if DSC is decided to be enabled. Works for both SST and MST.
Signed-off-by: Eryk Brol <eryk.b...@amd.com>
Signed-off-by: Mikita Lipski <mikita.lip...@amd.com>
Reviewed-by: Mikita Lipski <mikita.lip...@amd.com>
Acked-by: Eryk Brol <eryk.b...@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 93 +++++++++++++++++++
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ++
4 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5105e13a6088..0327e785e45c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4621,8 +4621,12 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
&stream->timing,
&stream->timing.dsc_cfg))
stream->timing.flags.DSC = 1;
+ /* Overwrite the stream flag if DSC is enabled through
debugfs */
if (aconnector->dsc_settings.dsc_clock_en)
stream->timing.flags.DSC = 1;
+ if (stream->timing.flags.DSC &&
aconnector->dsc_settings.dsc_slice_width)
+ stream->timing.dsc_cfg.num_slices_h =
DIV_ROUND_UP(stream->timing.h_addressable,
+
aconnector->dsc_settings.dsc_slice_width);
}
#endif
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 6f0a81f6f3c4..5b6f879a108c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -344,6 +344,7 @@ struct amdgpu_display_manager {
struct dsc_preferred_settings {
bool dsc_clock_en;
+ uint32_t dsc_slice_width;
};
struct amdgpu_dm_connector {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index d88620fa9d2b..df8b84aecc4d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1143,6 +1143,22 @@ static ssize_t dp_dsc_clock_en_write(struct file *f,
const char __user *buf,
return size;
}
+/* function: read DSC slice width parameter on the connector
+ *
+ * The read function: dp_dsc_slice_width_read
+ * returns dsc slice width used in the current configuration
+ * The return is an integer: 0 or other positive number
+ *
+ * Access the status with the following command:
+ *
+ * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
+ *
+ * 0 - means that DSC is disabled
+ *
+ * Any other number more than zero represents the
+ * slice width currently used by DSC in pixels
+ *
+ */
static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
@@ -1200,6 +1216,82 @@ static ssize_t dp_dsc_slice_width_read(struct file *f,
char __user *buf,
return result;
}
+/* function: write DSC slice width parameter
+ *
+ * The write function: dp_dsc_slice_width_write
+ * overwrites automatically generated DSC configuration
+ * of slice width.
+ *
+ * The user has to write the slice width divisible by the
+ * picture width.
+ *
+ * Also the user has to write width in hexidecimal
+ * rather than in decimal.
+ *
+ * Writing DSC settings is done with the following command:
+ * - To force overwrite slice width: (example sets to 1920 pixels)
+ *
+ * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
+ *
+ * - To stop overwriting and let driver find the optimal size,
+ * set the width to zero:
+ *
+ * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
+ *
+ */
+static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+ struct pipe_ctx *pipe_ctx;
+ int i;
+ char *wr_buf = NULL;
+ uint32_t wr_buf_size = 42;
+ int max_param_num = 1;
+ long param[1] = {0};
+ uint8_t param_nums = 0;
+
+ if (size == 0)
+ return -EINVAL;
+
+ wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
+
+ if (!wr_buf) {
+ DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
+ return -ENOSPC;
+ }
+
+ if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
+ (long *)param, buf,
+ max_param_num,
+ ¶m_nums)) {
+ kfree(wr_buf);
+ return -EINVAL;
+ }
+
+ if (param_nums <= 0) {
+ DRM_DEBUG_DRIVER("user data not be read\n");
+ kfree(wr_buf);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe_ctx =
&aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ if (pipe_ctx && pipe_ctx->stream &&
+ pipe_ctx->stream->link == aconnector->dc_link)
+ break;
+ }
+
+ if (!pipe_ctx || !pipe_ctx->stream)
+ goto done;
+
+ aconnector->dsc_settings.dsc_slice_width = param[0];
+
+done:
+ kfree(wr_buf);
+ return size;
+}
+
static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
@@ -1560,6 +1652,7 @@ static const struct file_operations
dp_dsc_clock_en_debugfs_fops = {
static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
.owner = THIS_MODULE,
.read = dp_dsc_slice_width_read,
+ .write = dp_dsc_slice_width_write,
.llseek = default_llseek
};
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 8250c37abe40..2c10352fa514 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -472,6 +472,7 @@ struct dsc_mst_fairness_params {
bool compression_possible;
struct drm_dp_mst_port *port;
bool clock_overwrite;
+ uint32_t slice_width_overwrite;
};
struct dsc_mst_fairness_vars {
@@ -506,6 +507,10 @@ static void set_dsc_configs_from_fairness_vars(struct
dsc_mst_fairness_params *p
¶ms[i].timing->dsc_cfg)) {
params[i].timing->flags.DSC = 1;
params[i].timing->dsc_cfg.bits_per_pixel =
vars[i].bpp_x16;
+ if (params[i].slice_width_overwrite)
+ params[i].timing->dsc_cfg.num_slices_h =
DIV_ROUND_UP(
+
params[i].timing->h_addressable,
+
params[i].slice_width_overwrite);
} else {
params[i].timing->flags.DSC = 0;
}
@@ -722,6 +727,7 @@ static bool compute_mst_dsc_configs_for_link(struct
drm_atomic_state *state,
params[count].clock_overwrite =
aconnector->dsc_settings.dsc_clock_en;
if (params[count].clock_overwrite)
debugfs_overwrite = true;
+ params[count].slice_width_overwrite =
aconnector->dsc_settings.dsc_slice_width;
params[count].compression_possible =
stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
if (!dc_dsc_compute_bandwidth_range(
--
2.25.1
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