From: Lijo Lazar <lijo.la...@amd.com>
Use SOC15 API so that the register offset is calculated correctly.
Signed-off-by: Lijo Lazar <lijo.la...@amd.com>
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 048e21d202d4..204b069c587d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1642,7 +1642,7 @@ static int gfx_v9_4_3_mqd_init(struct amdgpu_ring *ring)
/* set static priority for a queue/ring */
gfx_v9_4_3_mqd_set_priority(ring, mqd);
- mqd->cp_hqd_quantum = RREG32(regCP_HQD_QUANTUM);
+ mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, regCP_HQD_QUANTUM);
/* map_queues packet doesn't need activate the queue,
* so only kiq need set this field.
--
2.39.2
