[PATCH 3/4] drm/amd/display: Set compbuf size to min at prep prevent overbook crb

[Qingqing Zhuo]

From: "Ma, Duncan" <dunca...@amd.com>

[Why]
Detbuffer size is dynamically set for dcn31x. At certain moment,
compbuf+(def size * num pipes) > config return buffer size causing
flickering. This is easily reproducible when MPO is
enabled with two displays.

[How]
At prepare BW, use the min comp buffer size. When it is to
optimize BW, set compbuf size back to maximum possible size.

Reviewed-by: Charlene Liu <charlene....@amd.com>
Acked-by: Qingqing Zhuo <qingqing.z...@amd.com>
Signed-off-by: Duncan Ma <dunca...@amd.com>
Reviewed-by: Harry Wentland <harry.wentl...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c   | 12 ++++++++++--
 .../gpu/drm/amd/display/dc/dcn315/dcn315_resource.c  |  1 +
 .../drm/amd/display/dc/dml/display_mode_structs.h    |  1 +
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 20a9cbb7c0a8..1ef880fed776 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1818,6 +1818,7 @@ void dcn20_prepare_bandwidth(
                struct dc_state *context)
 {
        struct hubbub *hubbub = dc->res_pool->hubbub;
+       unsigned int compbuf_size_kb = 0;
 
        dc->clk_mgr->funcs->update_clocks(
                        dc->clk_mgr,
@@ -1829,9 +1830,16 @@ void dcn20_prepare_bandwidth(
                                        &context->bw_ctx.bw.dcn.watermarks,
                                        
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
                                        false);
+
        /* decrease compbuf size */
-       if (hubbub->funcs->program_compbuf_size)
-               hubbub->funcs->program_compbuf_size(hubbub, 
context->bw_ctx.bw.dcn.compbuf_size_kb, false);
+       if (hubbub->funcs->program_compbuf_size) {
+               if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
+                       compbuf_size_kb = 
context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
+               else
+                       compbuf_size_kb = 
context->bw_ctx.bw.dcn.compbuf_size_kb;
+
+               hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, 
false);
+       }
 }
 
 void dcn20_optimize_bandwidth(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index f22158bb4b13..46b170e60a54 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -147,6 +147,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = {
        .hostvm_max_page_table_levels = 2,
        .rob_buffer_size_kbytes = 64,
        .det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE,
+       .min_comp_buffer_size_kbytes = DCN3_15_MIN_COMPBUF_SIZE_KB,
        .config_return_buffer_size_in_kbytes = 1024,
        .compressed_buffer_segment_size_in_kbytes = 64,
        .meta_fifo_size_in_kentries = 32,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 8f9f1d607f7c..59f0a61c33cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -141,6 +141,7 @@ struct _vcs_dpi_ip_params_st {
        unsigned int odm_capable;
        unsigned int rob_buffer_size_kbytes;
        unsigned int det_buffer_size_kbytes;
+       unsigned int min_comp_buffer_size_kbytes;
        unsigned int dpte_buffer_size_in_pte_reqs_luma;
        unsigned int dpte_buffer_size_in_pte_reqs_chroma;
        unsigned int pde_proc_buffer_size_64k_reqs;
-- 
2.25.1