On 10/26/2023 2:22 AM, Victor Lu wrote:
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0.
Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC
and amdgpu_device_xcc_wreg/rreg to to use the new xcc_id parameter.
v3: use W/RREG32_XCC to handle non-kiq case
v2: define amdg
nks,
Victor
From: Lazar, Lijo
Sent: Thursday, October 26, 2023 4:16 AM
To: Lu, Victor Cheng Chi (Victor) ;
amd-gfx@lists.freedesktop.org
Cc: Ming, Davis
Subject: Re: [PATCH 3/5] drm/amdgpu: Use correct KIQ MEC engine for gfx9.4.3
(v3)
On 10/26/2023 2:22 AM, Vict
On 10/26/2023 2:22 AM, Victor Lu wrote:
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0.
Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC
and amdgpu_device_xcc_wreg/rreg to to use the new xcc_id parameter.
v3: use W/RREG32_XCC to handle non-kiq case
v2: define amdg
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0.
Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC
and amdgpu_device_xcc_wreg/rreg to to use the new xcc_id parameter.
v3: use W/RREG32_XCC to handle non-kiq case
v2: define amdgpu_device_xcc_wreg/rreg instead of changing p
