From: Dillon Varone <dillon.var...@amd.com>
[WHY?]
Cannot only consider the MALL required from top pipes because of the MPO
case.
[HOW?]
Only count a pipe if it fits the following criteria:
1) does not have a top pipe (is the topmost pipe for that plane)
2) it does have a top pipe, but that pipe is associated with a different
plane
Reviewed-by: Nevenko Stupar <nevenko.stu...@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
Signed-off-by: Dillon Varone <dillon.var...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 5b928f3b719d..7feb8759e475 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1356,9 +1356,10 @@ static void dcn32_calculate_dlg_params(struct dc *dc,
struct dc_state *context,
context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes =
get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
/* MALL Allocation Sizes */
- /* count from active, top pipes only */
+ /* count from active, top pipes per plane only */
if (context->res_ctx.pipe_ctx[i].stream &&
context->res_ctx.pipe_ctx[i].plane_state &&
- context->res_ctx.pipe_ctx[i].top_pipe == NULL &&
+ (context->res_ctx.pipe_ctx[i].top_pipe == NULL
||
+ context->res_ctx.pipe_ctx[i].plane_state !=
context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&
context->res_ctx.pipe_ctx[i].prev_odm_pipe ==
NULL) {
/* SS: all active surfaces stored in MALL */
if
(context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM)
{
--
2.39.0
