From: Sung Joon Kim <sungjoon....@amd.com> [why] preOS will not support display mode programming and link training for UHBR rates.
[how] If we detect a sink that's UHBR capable, disable seamless boot Reviewed-by: Anthony Koo <anthony....@amd.com> Acked-by: Wayne Lin <wayne....@amd.com> Signed-off-by: Sung Joon Kim <sungjoon....@amd.com> --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a8eb286ee4ff..9f56b2743f80 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1838,6 +1838,9 @@ bool dc_validate_boot_timing(const struct dc *dc, return false; } + if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) + return false; + if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) { DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n"); return false; -- 2.37.3