[PATCH v9 2/5] drm/amdgpu: Add mqd support for the fence address

[Arunpravin Paneer Selvam]

- Add a field in struct v11_gfx_mqd for userqueue
  fence address.

- Assign fence gpu VA address to the userqueue mqd
  fence address fields.

v2: Remove the mask and replace with lower_32_bits (Christian)

Signed-off-by: Arunpravin Paneer Selvam <arunpravin.paneersel...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 11 +++++++++++
 drivers/gpu/drm/amd/include/v11_structs.h        |  4 ++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c 
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
index 6369a26fb07e..d8592cfef534 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
@@ -25,6 +25,7 @@
 #include "v11_structs.h"
 #include "mes_v11_0.h"
 #include "amdgpu_userqueue.h"
+#include "amdgpu_userq_fence.h"
 
 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE
 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE
@@ -204,6 +205,14 @@ static int mes_v11_0_userq_create_ctx_space(struct 
amdgpu_userq_mgr *uq_mgr,
        return 0;
 }
 
+static void mes_v11_0_userq_set_fence_space(struct amdgpu_usermode_queue 
*queue)
+{
+       struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr;
+
+       mqd->fenceaddress_lo = lower_32_bits(queue->fence_drv->gpu_addr);
+       mqd->fenceaddress_hi = upper_32_bits(queue->fence_drv->gpu_addr);
+}
+
 static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,
                                      struct drm_amdgpu_userq_in *args_in,
                                      struct amdgpu_usermode_queue *queue)
@@ -274,6 +283,8 @@ static int mes_v11_0_userq_mqd_create(struct 
amdgpu_userq_mgr *uq_mgr,
                goto free_mqd;
        }
 
+       mes_v11_0_userq_set_fence_space(queue);
+
        /* FW expects WPTR BOs to be mapped into GART */
        r = mes_v11_0_create_wptr_mapping(uq_mgr, queue, 
userq_props->wptr_gpu_addr);
        if (r) {
diff --git a/drivers/gpu/drm/amd/include/v11_structs.h 
b/drivers/gpu/drm/amd/include/v11_structs.h
index f8008270f813..797ce6a1e56e 100644
--- a/drivers/gpu/drm/amd/include/v11_structs.h
+++ b/drivers/gpu/drm/amd/include/v11_structs.h
@@ -535,8 +535,8 @@ struct v11_gfx_mqd {
        uint32_t reserved_507; // offset: 507  (0x1FB)
        uint32_t reserved_508; // offset: 508  (0x1FC)
        uint32_t reserved_509; // offset: 509  (0x1FD)
-       uint32_t reserved_510; // offset: 510  (0x1FE)
-       uint32_t reserved_511; // offset: 511  (0x1FF)
+       uint32_t fenceaddress_lo; // offset: 510  (0x1FE)
+       uint32_t fenceaddress_hi; // offset: 511  (0x1FF)
 };
 
 struct v11_sdma_mqd {
-- 
2.25.1