On Fri, Sep 7, 2018 at 5:55 AM, Bas Nieuwenhuizen
wrote:
> On Fri, Sep 7, 2018 at 6:51 AM Marek Olšák wrote:
>>
>> Hopefully this answers some questions.
>>
>> Other parameters that affect tiling layouts are GB_ADDR_CONFIG (all
>> chips) and MC_ARB_RAMCFG (GFX6-8 only), and those vary with each c
On Fri, Sep 7, 2018 at 6:51 AM Marek Olšák wrote:
>
> Hopefully this answers some questions.
>
> Other parameters that affect tiling layouts are GB_ADDR_CONFIG (all
> chips) and MC_ARB_RAMCFG (GFX6-8 only), and those vary with each chip.
For GFX6-GFX8:
From GB_ADDR_CONFIG addrlib only uses the pi
Hopefully this answers some questions.
Other parameters that affect tiling layouts are GB_ADDR_CONFIG (all
chips) and MC_ARB_RAMCFG (GFX6-8 only), and those vary with each chip.
Some 32bpp 1D tiling layouts are compatible across all chips (1D
display tiling is the same as SW_256B_D if Bpp == 4).
On Tue, Sep 04, 2018 at 09:36:01PM +0200, Bas Nieuwenhuizen wrote:
> On Tue, Sep 4, 2018 at 9:28 PM Daniel Vetter wrote:
> >
> > On Tue, Sep 4, 2018 at 8:31 PM, Bas Nieuwenhuizen
> > wrote:
> > > On Tue, Sep 4, 2018 at 8:27 PM Daniel Vetter wrote:
> > >>
> > >> On Tue, Sep 4, 2018 at 7:57 PM, Ba
On Tue, Sep 4, 2018 at 9:28 PM Daniel Vetter wrote:
>
> On Tue, Sep 4, 2018 at 8:31 PM, Bas Nieuwenhuizen
> wrote:
> > On Tue, Sep 4, 2018 at 8:27 PM Daniel Vetter wrote:
> >>
> >> On Tue, Sep 4, 2018 at 7:57 PM, Bas Nieuwenhuizen
> >> wrote:
> >> > On Tue, Sep 4, 2018 at 7:48 PM Christian Köni
On Tue, Sep 4, 2018 at 8:31 PM, Bas Nieuwenhuizen
wrote:
> On Tue, Sep 4, 2018 at 8:27 PM Daniel Vetter wrote:
>>
>> On Tue, Sep 4, 2018 at 7:57 PM, Bas Nieuwenhuizen
>> wrote:
>> > On Tue, Sep 4, 2018 at 7:48 PM Christian König
>> > wrote:
>> >>
>> >> Am 04.09.2018 um 18:37 schrieb Daniel Vett
On Tue, Sep 4, 2018 at 8:27 PM Daniel Vetter wrote:
>
> On Tue, Sep 4, 2018 at 7:57 PM, Bas Nieuwenhuizen
> wrote:
> > On Tue, Sep 4, 2018 at 7:48 PM Christian König
> > wrote:
> >>
> >> Am 04.09.2018 um 18:37 schrieb Daniel Vetter:
> >> > On Tue, Sep 4, 2018 at 5:52 PM, Bas Nieuwenhuizen
> >> >
On Tue, Sep 4, 2018 at 7:57 PM, Bas Nieuwenhuizen
wrote:
> On Tue, Sep 4, 2018 at 7:48 PM Christian König
> wrote:
>>
>> Am 04.09.2018 um 18:37 schrieb Daniel Vetter:
>> > On Tue, Sep 4, 2018 at 5:52 PM, Bas Nieuwenhuizen
>> > wrote:
>> >> On Tue, Sep 4, 2018 at 4:43 PM Daniel Vetter wrote:
>>
Am 04.09.2018 um 20:00 schrieb Bas Nieuwenhuizen:
On Tue, Sep 4, 2018 at 7:57 PM Bas Nieuwenhuizen
wrote:
On Tue, Sep 4, 2018 at 7:48 PM Christian König
wrote:
Am 04.09.2018 um 18:37 schrieb Daniel Vetter:
On Tue, Sep 4, 2018 at 5:52 PM, Bas Nieuwenhuizen
wrote:
On Tue, Sep 4, 2018 at 4:43
On Tue, Sep 4, 2018 at 7:57 PM Bas Nieuwenhuizen
wrote:
>
> On Tue, Sep 4, 2018 at 7:48 PM Christian König
> wrote:
> >
> > Am 04.09.2018 um 18:37 schrieb Daniel Vetter:
> > > On Tue, Sep 4, 2018 at 5:52 PM, Bas Nieuwenhuizen
> > > wrote:
> > >> On Tue, Sep 4, 2018 at 4:43 PM Daniel Vetter wrot
On Tue, Sep 4, 2018 at 7:48 PM Christian König
wrote:
>
> Am 04.09.2018 um 18:37 schrieb Daniel Vetter:
> > On Tue, Sep 4, 2018 at 5:52 PM, Bas Nieuwenhuizen
> > wrote:
> >> On Tue, Sep 4, 2018 at 4:43 PM Daniel Vetter wrote:
> >>> On Tue, Sep 4, 2018 at 3:33 PM, Bas Nieuwenhuizen
> >>> wrote:
Am 04.09.2018 um 18:37 schrieb Daniel Vetter:
On Tue, Sep 4, 2018 at 5:52 PM, Bas Nieuwenhuizen
wrote:
On Tue, Sep 4, 2018 at 4:43 PM Daniel Vetter wrote:
On Tue, Sep 4, 2018 at 3:33 PM, Bas Nieuwenhuizen
wrote:
On Tue, Sep 4, 2018 at 3:04 PM Daniel Vetter wrote:
On Tue, Sep 04, 2018 at 0
On Tue, Sep 4, 2018 at 5:52 PM, Bas Nieuwenhuizen
wrote:
> On Tue, Sep 4, 2018 at 4:43 PM Daniel Vetter wrote:
>>
>> On Tue, Sep 4, 2018 at 3:33 PM, Bas Nieuwenhuizen
>> wrote:
>> > On Tue, Sep 4, 2018 at 3:04 PM Daniel Vetter wrote:
>> >>
>> >> On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nie
On Tue, Sep 4, 2018 at 4:43 PM Daniel Vetter wrote:
>
> On Tue, Sep 4, 2018 at 3:33 PM, Bas Nieuwenhuizen
> wrote:
> > On Tue, Sep 4, 2018 at 3:04 PM Daniel Vetter wrote:
> >>
> >> On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
> >> > On Tue, Sep 4, 2018 at 2:26 PM Daniel Vet
On Tue, Sep 4, 2018 at 3:33 PM, Bas Nieuwenhuizen
wrote:
> On Tue, Sep 4, 2018 at 3:04 PM Daniel Vetter wrote:
>>
>> On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
>> > On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
>> > >
>> > > On Tue, Sep 04, 2018 at 12:44:19PM +0200,
On Tue, Sep 4, 2018 at 3:04 PM Daniel Vetter wrote:
>
> On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
> > On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
> > >
> > > On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> > > > Am 04.09.2018 um 12:15 schrieb Da
Am 04.09.2018 um 15:17 schrieb Daniel Vetter:
On Tue, Sep 4, 2018 at 3:12 PM, Christian König
wrote:
Am 04.09.2018 um 15:03 schrieb Daniel Vetter:
On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
On Tue, Sep 04, 2018 at 1
On Tue, Sep 4, 2018 at 3:12 PM, Christian König
wrote:
> Am 04.09.2018 um 15:03 schrieb Daniel Vetter:
>>
>> On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
>>>
>>> On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian
Am 04.09.2018 um 15:03 schrieb Daniel Vetter:
On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Hi,
On Tue, 4 Se
Am 04.09.2018 um 14:26 schrieb Daniel Vetter:
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Hi,
On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
wrote:
+/* The chip this is c
On Tue, Sep 04, 2018 at 02:33:02PM +0200, Bas Nieuwenhuizen wrote:
> On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
> >
> > On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> > > Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > > > Hi,
> > > >
> > > > On Tue, 4 Sep 2018 at 11:
Am 04.09.2018 um 14:22 schrieb Daniel Stone:
Hi,
On Tue, 4 Sep 2018 at 11:44, Christian König
wrote:
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Right. The conclusion, after people went through and started sorting
out the kinds of formats for which they would _actually_ export real
colour bu
+everyone again
On Tue, Sep 4, 2018 at 2:39 PM Bas Nieuwenhuizen
wrote:
>
> On Tue, Sep 4, 2018 at 2:22 PM Daniel Stone wrote:
> >
> > Hi,
> >
> > On Tue, 4 Sep 2018 at 11:44, Christian König
> > wrote:
> > > Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > > > Right. The conclusion, after peopl
On Tue, Sep 4, 2018 at 2:26 PM Daniel Vetter wrote:
>
> On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> > Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > > Hi,
> > >
> > > On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
> > > > On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuiz
On Tue, Sep 04, 2018 at 12:44:19PM +0200, Christian König wrote:
> Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > Hi,
> >
> > On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
> > > On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
> > > wrote:
> > > > +/* The chip this is compatible with.
>
Hi,
On Tue, 4 Sep 2018 at 11:44, Christian König
wrote:
> Am 04.09.2018 um 12:15 schrieb Daniel Stone:
> > Right. The conclusion, after people went through and started sorting
> > out the kinds of formats for which they would _actually_ export real
> > colour buffers for, that most vendors defini
On Tue, Sep 4, 2018 at 12:04 PM Daniel Vetter wrote:
>
> On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
> wrote:
> > This is an initial proposal for format modifiers for AMD hardware.
> >
> > It uses 48 bits including a chip generation, leaving 8 bits for
> > a format version number.
> >
> > O
Am 04.09.2018 um 12:15 schrieb Daniel Stone:
Hi,
On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
wrote:
+/* The chip this is compatible with.
+ *
+ * If compression is disabled, use
+ * - AMDGPU_CHIP_TAHITI for GFX6-GFX8
+ * - AMDGPU_C
Hi,
On Tue, 4 Sep 2018 at 11:05, Daniel Vetter wrote:
> On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
> wrote:
> > +/* The chip this is compatible with.
> > + *
> > + * If compression is disabled, use
> > + * - AMDGPU_CHIP_TAHITI for GFX6-GFX8
> > + * - AMDGPU_CHIP_VEGA10 for GFX9+
> >
On Tue, Sep 4, 2018 at 3:00 AM, Bas Nieuwenhuizen
wrote:
> This is an initial proposal for format modifiers for AMD hardware.
>
> It uses 48 bits including a chip generation, leaving 8 bits for
> a format version number.
>
> On gfx6-gfx8 we have all the fields influencing sample locations
> in mem
Am 04.09.2018 um 03:00 schrieb Bas Nieuwenhuizen:
This is an initial proposal for format modifiers for AMD hardware.
It uses 48 bits including a chip generation, leaving 8 bits for
a format version number.
I'm absolutely not an expert on this, but as far as I know the major
problem with this
This is an initial proposal for format modifiers for AMD hardware.
It uses 48 bits including a chip generation, leaving 8 bits for
a format version number.
On gfx6-gfx8 we have all the fields influencing sample locations
in memory.
Tile split bytes are optional for single sample buffers as no
ha
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