Hi! I learned that each pipe can manage multiple hardware queues from the previous discussion: https://lists.freedesktop.org/archives/amd-gfx/2018-February/019034.html . And I had a few questions about the details. I was wondering that how a pipe switches between the hardware queues belong to it: 1. Dose the pipe process a queue continuously until the queue is empty? Or Dose it use round-robin with time-sharing between those hardware queues? 2. If the former, is it possible that some hardware queues suffer from starvation? 3. The previous discussion said that, at the same time, only one kernel can be running on each pipe. If the pipe used round-robin, did it incur the "compute wave save/restore"(CWSR) when the pipe switch from a hardware queue that has a running kernel to another hardware queue?
_______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
