ao, Yintian
Sent: Tuesday, April 21, 2020 9:46 PM
To: Koenig, Christian ; Liu, Monk ;
He, Jacob ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: cleanup SPM VMID update
Hi Christian
Great. Then can you modify the patch according to Monk's suggestion?
We need this patch fo
d-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: cleanup SPM VMID update
> The problem is some fields are increased by hardware
What are you talking about? The bits control what is used in the MC interface,
there is no increment or anything here.
> I think at least we should apply one chan
: Re: [PATCH] drm/amdgpu: cleanup SPM VMID update
Hi Monk,
at least on Vega that should be fine. If the RLC should use anything else than
0 here we should update that together with the VMID.
Regards,
Christian.
Am 21.04.20 um 11:54 schrieb Liu, Monk:
Could only be that the firmware updates the
PM
To: Liu, Monk ; Koenig, Christian ;
Tao, Yintian ; He, Jacob ;
amd-gfx@lists.freedesktop.org
Cc: Gu, Frans
Subject: Re: [PATCH] drm/amdgpu: cleanup SPM VMID update
Hi Monk,
at least on Vega that should be fine. If the RLC should use anything else than
0 here we should update that together
ation Team |AMD
-Original Message-
From: Christian König
Sent: Tuesday, April 21, 2020 5:52 PM
To: Tao, Yintian ; Liu, Monk ; He, Jacob
; amd-gfx@lists.freedesktop.org
Cc: Gu, Frans
Subject: Re: [PATCH] drm/amdgpu: cleanup SPM VMID update
Am 21.04.20 um 11:45 schrieb Tao, Yi
Gu, Frans
Subject: Re: [PATCH] drm/amdgpu: cleanup SPM VMID update
Am 21.04.20 um 11:45 schrieb Tao, Yintian:
>
> -Original Message-
> From: Christian König
> Sent: 2020年4月21日 17:10
> To: Liu, Monk ; Tao, Yintian ;
> He, Jacob ; amd-gfx@lists.freedesktop.org
>
Am 21.04.20 um 11:45 schrieb Tao, Yintian:
-Original Message-
From: Christian König
Sent: 2020年4月21日 17:10
To: Liu, Monk ; Tao, Yintian ; He, Jacob
; amd-gfx@lists.freedesktop.org
Cc: Gu, Frans
Subject: [PATCH] drm/amdgpu: cleanup SPM VMID update
The RLC SPM configuration register co
Christian
Many fields looks not like going to be still value at all, e.g.:
RLC_SPM_PERF_CNTR 5 0x0 PERF_CNTR that is used by RLC for
memory transactions
By your change you always set above filed to 0, is it right ? I really doubt
it
Beside: to make SRIOV VF less painful ple
-Original Message-
From: Christian König
Sent: 2020年4月21日 17:10
To: Liu, Monk ; Tao, Yintian ; He, Jacob
; amd-gfx@lists.freedesktop.org
Cc: Gu, Frans
Subject: [PATCH] drm/amdgpu: cleanup SPM VMID update
The RLC SPM configuration register contains the information how the memory
acce
