On Wed, Mar 16, 2022 at 8:14 PM Peter Geis wrote:
>
> Good Evening,
>
> I apologize for raising this email chain from the dead, but there have
> been some developments that have introduced even more questions.
> I've looped the Rockchip mailing list into this too, as this affects
> rk356x, and
On Fri, Mar 18, 2022 at 4:35 AM Christian König
wrote:
>
>
>
> Am 18.03.22 um 08:51 schrieb Kever Yang:
>
>
> On 2022/3/17 20:19, Peter Geis wrote:
>
> On Wed, Mar 16, 2022 at 11:08 PM Kever Yang wrote:
>
> Hi Peter,
>
> On 2022/3/17 08:14, Peter Geis wrote:
>
> Good Evening,
>
> I apologize for
On Fri, Mar 18, 2022 at 8:31 AM Christian König
wrote:
>
> Am 18.03.22 um 12:24 schrieb Peter Geis:
> > On Fri, Mar 18, 2022 at 4:35 AM Christian König
> > wrote:
> >>
> >>
> >> Am 18.03.22 um 08:51 schrieb Kever Yang:
> >>
> >>
> >> On 2022/3/17 20:19, Peter Geis wrote:
> >>
> >> On Wed, Mar
On 2022/3/17 20:19, Peter Geis wrote:
On Wed, Mar 16, 2022 at 11:08 PM Kever Yang wrote:
Hi Peter,
On 2022/3/17 08:14, Peter Geis wrote:
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments that have introduced even more questions.
Am 18.03.22 um 12:24 schrieb Peter Geis:
On Fri, Mar 18, 2022 at 4:35 AM Christian König
wrote:
Am 18.03.22 um 08:51 schrieb Kever Yang:
On 2022/3/17 20:19, Peter Geis wrote:
On Wed, Mar 16, 2022 at 11:08 PM Kever Yang wrote:
Hi Peter,
On 2022/3/17 08:14, Peter Geis wrote:
Good
Am 18.03.22 um 08:51 schrieb Kever Yang:
On 2022/3/17 20:19, Peter Geis wrote:
On Wed, Mar 16, 2022 at 11:08 PM Kever Yang
wrote:
Hi Peter,
On 2022/3/17 08:14, Peter Geis wrote:
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments
On Thu, Mar 17, 2022 at 5:15 AM Christian König
wrote:
>
> Hi Peter,
>
> Am 17.03.22 um 01:14 schrieb Peter Geis:
> > Good Evening,
> >
> > I apologize for raising this email chain from the dead, but there have
> > been some developments that have introduced even more questions.
> > I've looped
On Thu, Mar 17, 2022 at 9:17 AM Robin Murphy wrote:
>
> On 2022-03-17 12:26, Peter Geis wrote:
> > On Thu, Mar 17, 2022 at 6:37 AM Robin Murphy wrote:
> >>
> >> On 2022-03-17 00:14, Peter Geis wrote:
> >>> Good Evening,
I've added the Designware driver maintainers, since the Rockchip host
On 2022-03-17 12:26, Peter Geis wrote:
On Thu, Mar 17, 2022 at 6:37 AM Robin Murphy wrote:
On 2022-03-17 00:14, Peter Geis wrote:
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments that have introduced even more questions.
I've looped
On Wed, Mar 16, 2022 at 11:08 PM Kever Yang wrote:
>
> Hi Peter,
>
> On 2022/3/17 08:14, Peter Geis wrote:
> > Good Evening,
> >
> > I apologize for raising this email chain from the dead, but there have
> > been some developments that have introduced even more questions.
> > I've looped the
On 2022-03-17 00:14, Peter Geis wrote:
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments that have introduced even more questions.
I've looped the Rockchip mailing list into this too, as this affects
rk356x, and likely the upcoming
On Thu, Mar 17, 2022 at 6:37 AM Robin Murphy wrote:
>
> On 2022-03-17 00:14, Peter Geis wrote:
> > Good Evening,
> >
> > I apologize for raising this email chain from the dead, but there have
> > been some developments that have introduced even more questions.
> > I've looped the Rockchip mailing
On Thu, Mar 17, 2022 at 5:15 AM Christian König
wrote:
>
> Hi Peter,
>
> Am 17.03.22 um 01:14 schrieb Peter Geis:
> > Good Evening,
> >
> > I apologize for raising this email chain from the dead, but there have
> > been some developments that have introduced even more questions.
> > I've looped
Am 17.03.22 um 13:26 schrieb Peter Geis:
On Thu, Mar 17, 2022 at 6:37 AM Robin Murphy wrote:
On 2022-03-17 00:14, Peter Geis wrote:
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments that have introduced even more questions.
I've
Hi Peter,
Am 17.03.22 um 01:14 schrieb Peter Geis:
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments that have introduced even more questions.
I've looped the Rockchip mailing list into this too, as this affects
rk356x, and likely the
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments that have introduced even more questions.
I've looped the Rockchip mailing list into this too, as this affects
rk356x, and likely the upcoming rk3588 if [1] is to be believed.
TLDR for
Hi Peter,
On 2022/3/17 08:14, Peter Geis wrote:
Good Evening,
I apologize for raising this email chain from the dead, but there have
been some developments that have introduced even more questions.
I've looped the Rockchip mailing list into this too, as this affects
rk356x, and likely the
On 2021-05-26 10:42, Christian König wrote:
Hi Robin,
Am 25.05.21 um 22:09 schrieb Robin Murphy:
On 2021-05-25 14:05, Alex Deucher wrote:
On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
On Tue, May 25, 2021 at 8:47 AM Alex Deucher
wrote:
On Tue, May 25, 2021 at 8:42 AM Peter Geis
Hi Robin,
Am 26.05.21 um 12:59 schrieb Robin Murphy:
On 2021-05-26 10:42, Christian König wrote:
Hi Robin,
Am 25.05.21 um 22:09 schrieb Robin Murphy:
On 2021-05-25 14:05, Alex Deucher wrote:
On Tue, May 25, 2021 at 8:56 AM Peter Geis
wrote:
On Tue, May 25, 2021 at 8:47 AM Alex Deucher
Hi Robin,
Am 25.05.21 um 22:09 schrieb Robin Murphy:
On 2021-05-25 14:05, Alex Deucher wrote:
On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
On Tue, May 25, 2021 at 8:47 AM Alex Deucher
wrote:
On Tue, May 25, 2021 at 8:42 AM Peter Geis
wrote:
Good Evening,
I am stress testing
On 2021-05-25 14:05, Alex Deucher wrote:
On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
Good Evening,
I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
Am 25.05.21 um 16:19 schrieb Peter Geis:
On Tue, May 25, 2021 at 10:08 AM Christian König
wrote:
Hi Peter,
some comment additionally what Alex said.
Am 25.05.21 um 04:34 schrieb Peter Geis:
[SNIP]
Memory at 30090 (64-bit, non-prefetchable) [size=128K]
This here...
On Tue, May 25, 2021 at 10:08 AM Christian König
wrote:
>
> Hi Peter,
>
> some comment additionally what Alex said.
>
> Am 25.05.21 um 04:34 schrieb Peter Geis:
> > Good Evening,
> >
> > I am stress testing the pcie controller on the rk3566-quartz64 prototype
> > SBC.
> > This device has 1GB
Hi Peter,
some comment additionally what Alex said.
Am 25.05.21 um 04:34 schrieb Peter Geis:
Good Evening,
I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
This device has 1GB available at <0x3 0x> for the PCIe
controller, which makes a dGPU theoretically
On Tue, May 25, 2021 at 9:05 AM Alex Deucher wrote:
>
> On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
> >
> > On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
> > >
> > > On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
> > > >
> > > > Good Evening,
> > > >
> > > > I am stress testing
On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
>
> On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
> >
> > On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
> > >
> > > Good Evening,
> > >
> > > I am stress testing the pcie controller on the rk3566-quartz64 prototype
> > > SBC.
> > >
On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote:
>
> On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
> >
> > Good Evening,
> >
> > I am stress testing the pcie controller on the rk3566-quartz64 prototype
> > SBC.
> > This device has 1GB available at <0x3 0x> for the PCIe
> >
On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote:
>
> Good Evening,
>
> I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
> This device has 1GB available at <0x3 0x> for the PCIe
> controller, which makes a dGPU theoretically possible.
> While attempting to
Good Evening,
I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC.
This device has 1GB available at <0x3 0x> for the PCIe
controller, which makes a dGPU theoretically possible.
While attempting to light off a HD7570 card I manage to get a modeset
console, but
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