[Amforth] External Interrupt Mask Register

2018-11-04 Thread Jan Kromhout
Hi, I have a strange behavior and can’t explain. The ATmega328P supports two external interrupts which are individually enabled by setting bits INT1 and INT0 in the External Interrupt Mask Register (EIMSK) The address is $1d. When I look to the documentation te bits 0 and 1 are R/W and the other

Re: [Amforth] Question about Timer1 - is there a bug?

2018-11-04 Thread Matthias Trute
> My leaving question is the word “f_cpu” in the code of Timer1.frt. > When I execute it I get two values on the stack. It's the current clock the controller is running at. It's a double cell number, since the 16bit controllers run too fast to keep this number in a single cell. Matthias ___