Re: [Amforth] External Interrupt Mask Register

2018-11-05 Thread Jan Kromhout via Amforth-devel
Hi, Thanks Mathias, problem is solved. My application is running as it should. Cheers, Jan > Op 5 nov. 2018, om 20:04 heeft Matthias Trute het volgende > geschreven: > > Hi, > >> When I do the command $1d c@ . I get a value of 0001000. How is that >> possible? Or do I something wrong? > >

Re: [Amforth] External Interrupt Mask Register

2018-11-05 Thread Matthias Trute
Hi, > When I do the command $1d c@ . I get a value of 0001000. How is that > possible? Or do I something wrong? Historically Atmel defined 32 special addresses that together with certain opcodes that are used for some IO or CPU relevant things (e.g. the machine status register which is one of th

Re: [Amforth] External Interrupt Mask Register

2018-11-05 Thread Jan Kromhout via Amforth-devel
Tristan, I have found the datasheet. Cheers, Jan Verstuurd vanaf mijn iPad > Op 5 nov. 2018 om 11:26 heeft Jan Kromhout het > volgende geschreven: > > Tristan, > > Thanks again for your hulp. > Please can you provide me the link to download the datasheet your mention. > When I look to the

Re: [Amforth] External Interrupt Mask Register

2018-11-05 Thread Jan Kromhout
Tristan, Thanks again for your hulp. Please can you provide me the link to download the datasheet your mention. When I look to the datasheets they only have about 25 pages!!. Cheers, Jan > Op 5 nov. 2018, om 09:47 heeft Tristan Williams het > volgende geschreven: > > Jan, > >> The addres

Re: [Amforth] External Interrupt Mask Register

2018-11-05 Thread Tristan Williams
Jan, > The address is $1d. When I look to the documentation te bits 0 and 1 > are R/W and the other bits are only Read (With a initial value of 0) > When I do the command $1d c@ . I get a value of 0001000. How is that > possible? Or do I something wrong? The answer to this lies in the memory map

[Amforth] External Interrupt Mask Register

2018-11-04 Thread Jan Kromhout
Hi, I have a strange behavior and can’t explain. The ATmega328P supports two external interrupts which are individually enabled by setting bits INT1 and INT0 in the External Interrupt Mask Register (EIMSK) The address is $1d. When I look to the documentation te bits 0 and 1 are R/W and the other