Hi Jon,
The description of the ARM barrier operations is not entirely accurate.
The DMB does not guarantee completion of anything - it only enforces
ordering.
I.e.
---
ldr access to clear an interrupt source
DMB
CPSIE i
---
does not guarantee that the interrupt line is not still live when the
On 11/13/2012 01:24 AM, Nicolas Pitre wrote:
There are several serious mistakes in your assembly example.
Thanks for the feedback! Appreciated. Comments below...
|START_FUNC(opal_atomic_add_32)
| push{r4-r7}
Why r4 to r7? You're using only r4 below.
Ah. Because in the rest of
On 14 November 2012 06:21, Jon Masters j...@redhat.com wrote:
On 11/13/2012 01:24 AM, Nicolas Pitre wrote:
There are several serious mistakes in your assembly example.
Thanks for the feedback! Appreciated. Comments below...
|START_FUNC(opal_atomic_add_32)
| push{r4-r7}
Why r4
Hi everyone,
I wrote the following little summary of ARM atomics:
http://www.jonmasters.org/blog/2012/11/13/arm-atomic-operations/
It's not terribly comprehensive, but you could use it to understand what
I did in OpenMPI, and how to poke at other packages.
Jon.
