Re: [ARTIQ] clock recovery on Metlino and Kasli

Well, one can do this, there were discussion about replacing of VCXO with internall PLL (there is Xilinx note about it) But it requires additional work in gateware and it is not trivial to make it working reliably. Greg -Original Message- From: Sébastien Bourdeauducq

Re: [ARTIQ] clock recovery on Metlino and Kasli

OK On 30 June 2016 at 10:50, Sébastien Bourdeauducq wrote: > On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote: > >> In case of WR it already worked quite well 6 years ago but later on this >> circuit was modified several times:) >> All the time little things. >> So

Re: [ARTIQ] clock recovery on Metlino and Kasli

On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote: In case of WR it already worked quite well 6 years ago but later on this circuit was modified several times:) All the time little things. So since we have more important things to do I'd leave it as it is. Since we are not going