Two comments and a clarification:

- DAC is AD9154, not AD9145
- at the bottom of page 2, it specifies f_max = 300 MHz, but I assume this is 
not correct?  What I think should be happening is a 48-bit phase accumulator 
with frequency tuning word specified by f (which is a linear interpolator, 
allowing for frequency chirps) and the constant offset p, the value of which is 
then run into CORDIC (or equivalent) to calculate sine or cosine.  Is this 
right?
- a clarification: is it correct that u, a, and f are constant between updates 
at f_DAC/16?  i.e., they maintain their values for 16 time points, then their 
values update to the next calculated value from the interpolator?  In other 
words, the interpolators generate new values for u, a, f only every 16 time 
points?  

Best,
Daniel

> -----Original Message-----
> From: j arl [mailto:joe.britton....@gmail.com]
> Sent: Thursday, July 28, 2016 3:14 PM
> To: artiq@lists.m-labs.hk; Sébastien Bourdeauducq
> <sebastien.bourdeaud...@gmail.com>; Robert Jördens <r...@m-labs.hk>;
> Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov>; jase...@gmail.com;
> camaca...@gmail.com
> Subject: proposed DAC gateware
> 
> Dear prospective Sayma users, please comment on the attached gateware
> and ARTIQ-integration specification. It is intended to be stand-alone and
> make minimal reference to the microTCA hardware. The aim is to provide
> isolation of the gateware development from broader Sayma/Metlino
> system. Detailed specification of the other components are forthcoming.
> 
> Many thanks to long conversations with Robert Jordens and Sebastien
> Bourdeauducq (m-labs), Jonathan Mizrahi (JQI) and Daniel Slichter (NIST
> Boulder). Huge props to developers of the NIST PDQ system Ryan Bowler (U.
> Washington) and Jason Heidecker. And to Robert Jordens
> (m-labs.hk) who developed its successor PDQ2.
> 
> -Joe
> 
> -------
> Joe Britton
> Sensors and Electron Devices
> Army Research Lab
> 2800 Powder Mill Rd
> Adelphi, MD 20783
> 301-394-3130
> joseph.w.britton5....@mail.mil
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