On Thursday, August 09, 2018 03:15 AM, Thomas Harty via ARTIQ wrote:
it's a big FPGA and IIRC we're not
really pushing the resources limits yet (but maybe I'm wrong about
that?), so it's not clear that's actually a problem. I get that
multi-hour compile times are death, but at least we haven't
> The coarse f0 DUC (as per the proposal) would be tens of multipliers
> instead of eight CORDICs+accumulators. We'd need an exploratory
> project to get hard numbers for the resource trade of.
I think a short exploratory project would be a good idea, as I have no real
means of making an
