Hi,
> Supporting this KC705 scheme is
> more gateware development and one more configuration that needs to be
> documented, packaged and maintained. Maintainance means that we need to
> check regularly (preferably automatically) that it keeps working when we
> modify ARTIQ and fix any bugs that p
> ..., and we might spin up some in-house boards for multichannel DAC over SPI.
FYI, the Zotino and Novogorny DAC/ADC EEMs are now funded (Oxford/Freiburg) and
being designed by WUT. They should be ready in ~12weeks. We're planning to
contract M-Labs to provide full support for them.
The draft
@lists.m-labs.hk] On Behalf Of Thomas Harty
via ARTIQ
Sent: Friday, March 10, 2017 12:56 PM
To: artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] ARTIQ Digest, Vol 34, Issue 3
> ..., and we might spin up some in-house boards for multichannel DAC over SPI.
FYI, the Zotino and Novogorny DAC/ADC EEMs are
HDCI carrier as a short-term solution.
-Original Message-
From: ARTIQ
[mailto:artiq-boun...@lists.m-labs.hk<mailto:artiq-boun...@lists.m-labs.hk>] On
Behalf Of Thomas Harty via ARTIQ
Sent: Friday, March 10, 2017 12:56 PM
To: artiq@lists.m-labs.hk<mailto:artiq@lists.m-labs.hk>
Sub
Sébastien,
Given the relatively low cost of the Artix-7 FPGAs, my preference is generally
to go as big and as fast as reasonably possible. I don't want to find that, for
example, we can't fit a hard FPU/fancy servo on Kasli because we saved $50 on
the FPGA. Also, since gateware development is u
sage: 2
> Date: Thu, 29 Jun 2017 12:27:17 +0000
> From: "Slichter, Daniel H. (Fed)"
> To: "'artiq@lists.m-labs.hk'"
> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6
> Message-ID:
>
>
>
> Content-Type: text/plain; charset=&
Dear all,
The first artiq hardware is now available to buy!
You can now buy the following boards (fully populated and tested, complete with
aluminium front panels):
VHDCI_carrier
BNC_DIO
SMA_DIO
RJ45_DIO
See https://github.com/m-labs/sinara/wiki for more info about these boards.
Note that all
Joe,
I'm still waiting for my Sayma to arrive back from Poland. I'll have a look at
this asap once it arrives, so long as that I'm not blocked by other issues like
ser-wb failures.
T
Dr Thomas Harty
Junior Research Fellow, St John's College
University of Oxford, Department of Physics
The C
> any objections to supporting only the RTIO clock frequency (currently 150MHz)
> at the Sayma input, instead of 100MHz?
Assuming you mean "supporting" in the sense of which bitstreams M-Labs will
build and test, I'm fine with that.
IIRC, changing reference frequency is pretty easy and only r
> use the DAC interpolation modes (2X, 4X, 8X) if the goal is simply to improve
> spectral purity.
It would be good to get the interpolation running, both to improve spectral
purity and to put the hardware through its paces before we move on to the next
design revision (I'd love to see synchro
> Fine adjustment of SAWG f0 by RTIO and local DSP is the planned path
> for dynamically compensating for time-variation of the Coherent
> Paladin laser repetition rate. Could the resolution of the the f0 NCO
> be defined parametrically? This could enable relatively
> straightforward switching
> The primary application here would be the driving of AOMs centered at 220 MHz
> (which could be done at 600 MSPS in theory) or 330 MHz (much harder to avoid
> Nyquist images at 600 MSPS). We would most likely want 1 GSPS, with an RTIO
> clock of 125 MHz, which also aids compatibility with our ot
x27;s Topics:
1. Re: ARTIQ Digest, Vol 50, Issue 7 (Robert Jördens)
--------------
Message: 1
Date: Wed, 18 Jul 2018 19:24:11 +0200
From: Robert Jördens
To: artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] ARTIQ Digest, Vol 50, Issue 7
Message-ID:
+44 (0)7986 375 052
Lab: +44 (0)1865 272 572
From: Sébastien Bourdeauducq
Sent: 09 August 2018 02:53:43
To: Thomas Harty; artiq@lists.m-labs.hk; Robert Jördens
Subject: SAWG
On Thursday, August 09, 2018 03:15 AM, Thomas Harty via ARTIQ wrote:
> it's a
ry
Parks Road, Oxford, OX1 3PU
Mob: +44 (0)7986 375 052
Lab: +44 (0)1865 272 572
From: Sébastien Bourdeauducq
Sent: 09 August 2018 02:53:43
To: Thomas Harty; artiq@lists.m-labs.hk; Robert Jördens
Subject: SAWG
On Thursday, August 09, 2018 03:15 AM, Thomas Harty via ARTIQ wrote:
> it'
> Debugging is one aspect. But a ballpark estimate for the resource
usage increase when going from 600 MHz to 1 GHz and adding all the
bells and whistles that people said they need would be 2x the logic.
Good to know, thanks.
Where are we in terms of resource usage with the current design? What
> IIRC resource usage is around 50%-60% now. But have a look at any Vivado run.
> It gets increasingly hard anywhere between 70 and 90% depending on the
> routing.
Thanks for clarifying that.
Okay, so it really is the case that with the current design getting the 1GSPS
data rate, 8-channel S
> All correct, except the last bit: the digital equivalent of DC/LO
> leakage is less than one LSB. There will be a spur but it's well controlled.
Remind me, for the current design, what's a 1 LSB spur in dBc? How does that
scale with the width parameters?
> How low do the other spurs have to
> I have spelled out in previous emails why I think there is a very compelling
> physics case for us to be able to run at 800 MSPS/1 GSPS (8x f_rtio at
> 100 MHz or 125 MHz RTIO freq, respectively),
> At intermediate field (119 G), relevant 9Be+ transitions are between 1 GHz
> and 1.4 GHz, so usin
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