> The coarse f0 DUC (as per the proposal) would be tens of multipliers
> instead of eight CORDICs+accumulators. We'd need an exploratory
> project to get hard numbers for the resource trade of.
I think a short exploratory project would be a good idea, as I have no real
means of making an informe
On Wed, Aug 8, 2018 at 9:15 PM Thomas Harty
wrote:
> I think a short exploratory project would be a good idea, as I have no real
> means of making an informed decision about where to shoot for on the
> performance/flexibility v complexity scale. 8 CORDICS + accumulators on 8
> channels sounds l
> Debugging is one aspect. But a ballpark estimate for the resource
usage increase when going from 600 MHz to 1 GHz and adding all the
bells and whistles that people said they need would be 2x the logic.
Good to know, thanks.
Where are we in terms of resource usage with the current design? What
> What "bells and whistles" do you mean? Do you mean things like fancy
> modulation/demodulation schemes for PDH locks etc? Let's have a bells and
> whistles list and see what we can agree to cull.
Agreed, I think a list of the current "bells and whistles" would help a lot in
terms of thinking
On Thu, Aug 9, 2018 at 11:56 AM Thomas Harty
wrote:
> Where are we in terms of resource usage with the current design? What's a
> rough upper bound on how high we can push the resource utilization on an FPGA
> for this kind of design before timing closure/compile times/etc becomes a
> nightmare
> IIRC resource usage is around 50%-60% now. But have a look at any Vivado run.
> It gets increasingly hard anywhere between 70 and 90% depending on the
> routing.
Thanks for clarifying that.
Okay, so it really is the case that with the current design getting the 1GSPS
data rate, 8-channel S
> All correct, except the last bit: the digital equivalent of DC/LO
> leakage is less than one LSB. There will be a spur but it's well controlled.
Remind me, for the current design, what's a 1 LSB spur in dBc? How does that
scale with the width parameters?
> How low do the other spurs have to
On Sat, Aug 11, 2018 at 12:28 PM Thomas Harty
wrote:
> Remind me, for the current design, what's a 1 LSB spur in dBc? How does that
> scale with the width parameters?
1 LSB is -96 dBc.
But e.g. the AA filter is currently -58 dB stopband.
> > And regarding the benefit I don't see a reason why t
On Sat, Aug 11, 2018 at 12:12 PM Thomas Harty
wrote:
> - Moninj: Chris B/David N will be able to give a better-informed view on this
> than me, but my feeling is that moninj isn't actually that useful for the
> SAWG. What would SAWG moninj include? Leaving aside the work/funding required
> to i
> I have spelled out in previous emails why I think there is a very compelling
> physics case for us to be able to run at 800 MSPS/1 GSPS (8x f_rtio at
> 100 MHz or 125 MHz RTIO freq, respectively),
> At intermediate field (119 G), relevant 9Be+ transitions are between 1 GHz
> and 1.4 GHz, so usin
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