Hi,
Thanks Florent, I didn't find the Vivado command to generate raw
binaries in the manual.
Direct load with xc3sprog still does not work, but the bitgen options
solve another problem: booting the FPGA from flash was also broken.
Sébastien
On 03/29/2015 06:21 PM, Florent Kermarrec wrote:
Here is a patch that should add .bin generation on the KC705 with Vivado
(Sorry I don't have a machine with Vivado installed with me, so I'm not
able to test, but I've used parameters I use for another design).
There was also an issue with bitgen_opt with ISE, so it will maybe solve
your second
Hi,
Seems to work here, thanks for fixing!
I found two other bugs while testing:
* Vivado fails to generate the .bin raw binary bitstream file:
https://github.com/m-labs/migen/issues/9
This breaks loading the bitstream into flash wish xc3sprog. Building
with ISE works around the problem.
*
Hi,
the issue should be fixed. I found 2 issues:
- the number of rows for the KC705's DDR3 was not correct (we were using
rowbits=16 instead of 14).
- the current mapping we are using on the Wishbone bus limit us to 256MB.
(The real size of the KC705's DDR3 is 1GB, it's now artificially limited
Still no luck getting Artiq to run on the KC705. I pulled and built last
night at 7p Colorado time. Here's a transcript. -Joe
*rabi@vboxartiq:~/artiq-dev/misoc$ git pull*
*rabi@vboxartiq:~/artiq-dev/artiq$ git pull*
*rabi@vboxartiq:~/artiq-dev/migen$ git pull*
*rabi@vboxartiq:~/artiq-dev/misoc$
Can you run git checkout . in every repository to revert such
modifications (you may want to use git diff before to make
sure you are not deleting anything important), and try again?
There were some local modification. I've reverted to the master and will
rebuild.
