@lists.m-labs.hk; Sébastien Bourdeauducq
<sebastien.bourdeaud...@gmail.com>; Robert Jördens <r...@m-labs.hk>; Slichter,
Daniel H. (Fed) <daniel.slich...@nist.gov>; jase...@gmail.com;
camaca...@gmail.com
Subject: [ARTIQ] proposed DAC gateware
Dear prospective Sayma use
Two comments and a clarification:
- DAC is AD9154, not AD9145
- at the bottom of page 2, it specifies f_max = 300 MHz, but I assume this is
not correct? What I think should be happening is a 48-bit phase accumulator
with frequency tuning word specified by f (which is a linear interpolator,
