On 09/05/2014 04:07 AM, Sébastien Bourdeauducq wrote:
>> Temperature and/or vivado-ise differences change it by at most one bit
>> time.
>
> I guess you meant a IODELAY tap?
Yes.
Robert.
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On 09/05/2014 01:39 PM, Robert Jordens wrote:
> Works fine here. The windows look good with vivado as well as ise.
Great!
> Temperature and/or vivado-ise differences change it by at most one bit
> time.
I guess you meant a IODELAY tap?
Sébastien
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On 09/03/2014 01:56 AM, Sébastien Bourdeauducq wrote:
> Please test on yours and report your results - all the code is committed
> in MiSoC, so you should be able to build and flash everything with:
Works fine here. The windows look good with vivado as well as ise.
Temperature and/or vivado-ise di
> > Please test on yours and report your results - all the code is
> > committed in MiSoC, so you should be able to build and flash everything
> > with:
> I guess so far I have been the only one here at NIST regularly reading the
> code, building, and testing it.
> It would be great if someone
On 09/04/2014 08:46 AM, Robert Jordens wrote:
>> The write delay on the data lines is set to the write leveling DQS delay
>> minus half a bit time to meet the DQS/DQ setup/hold requirements. At
>> this point, we have functional writes to the SDRAM.
>
> Why don't you place them in the middle of the
On 09/03/2014 01:56 AM, Sébastien Bourdeauducq wrote:
> Florent and I got the full DDR3 SODIMM to work on the KC705 board. The
> peak bandwidth is 64Gbps, which I think sets the record of the fastest
> open source SDRAM controller :)
Congratulations! Impressive tour de force.
> Please test on you
