Nay. Many, many instructions are not atomic. On a single CPU, yes. For
multiple CPUs, not atomic. Until the z13 (?), for example, NI, OI and XI
were interruptible within a reference to a single byte. NI is actually
fetch, AND, store. It could be interrupted between the fetch and the store.
So two
I believe the only true atomic instructions are CS and CSD. PLO is considered
atomic when using the same lock. Concurrency is only guaranteed with some sort
of lock which is to expensive to implement for every instruction and for
storage being referenced / modified. The odds of a single
On 7/30/2017 6:32 PM, Phil Smith wrote:
Robert Netzloff wrote:
Not sure, but is not MVCL interruptible?
Yes, that one is. Good catch! I've seen it happen, too. Makes sense: you MVCL
more than one page, and one of them is paged out, so it has to stop while the
page fault happens and it comes
Robert Netzloff wrote:
>Not sure, but is not MVCL interruptible?
Yes, that one is. Good catch! I've seen it happen, too. Makes sense: you MVCL
more than one page, and one of them is paged out, so it has to stop while the
page fault happens and it comes in. CLCL too, of course. And MVCLE and
On 7/30/17, Phil Smith wrote:
> Charles Mills wrote, in part:
>>The effect of multiple CPUs on a multi-task program is even worse than the
>>load, add, store example above. With two CPUs, it is possible for even
>>single machine instructions to interleave. So if one task
Charles Mills wrote, in part:
>The effect of multiple CPUs on a multi-task program is even worse than the
>load, add, store example above. With two CPUs, it is possible for even
>single machine instructions to interleave. So if one task executes MVC
>FOO,=C'Now is the time for all good men to come
>Is the target of an EXECUTE considered to be an executable
>instruction if it's in EXECUTABLE=NO storage?
yes
Peter Relson
z/OS Core Technology Design
>From the application's point of view -- and you must take this into
consideration in designing a multi-task application -- all tasks (TCBs) may
run "at the same time" even though there are more tasks than CPUs. If a task
loads a word, adds one to it, and stores it back, you have to consider that
>My understanding is a Task (TCB) in an address spaces always requires a CPU to
>be assigned/associated with.
Yes.
> So with Logical/Virtual CPUS, can I have more TCBS, actively dispatched at
> the same time in the same Address Space, than the Physical CPUs ?
No. A single physical CP can only