On 4/19/2022 7:13 PM, Bob Raicer wrote:
Having the ability to assemble quadword aligned 128-bit items for
use with these instructions would be helpful.
We define quadword-aligned storage areas all the time. For example:
Field1 DC LQ'0'
Field2 DC LQ'0'
Of course, you need to specify the
I thought I'd bring an explanation
to what's going on here...
Let's consider the following short
C example (just to have something
to compile):
foo()
{
unsigned char ovfl;
int ccpm, carrybit;
ccpm = bar(); carrybit=bar2();
ovfl = (ccpm & carrybit) != 0;
blah(ovfl);
}
The
A couple of more general instructions which require quadword aligned
storage operands and 128-bit values in even-odd pairs of 64-bit
GPRs:
Compare Double and Swap (CDSG)
Compare and Swap and Store (CSST)
Having the ability to assemble quadword aligned 128-bit items for
use with these
On Apr 19, 2022, at 17:57:23, Bernd Oppolzer wrote:
>
> LPR: if the register contains 0x8000, IMO the result will be zero (and
> overflow),
>
I'd expect 0x8000, with overflow.
> so you're right ... this will lead to a zero result. IMO, the overflow will
> be ignored.
>
C
Ok, I had to read the manual (PoOp), to see how LPR and LCR actually work
and the OP probably should post the definitions of ccpm and carrybit.
LPR: if the register contains 0x8000, IMO the result will be zero
(and overflow),
so you're right ... this will lead to a zero result. IMO, the
On Apr 19, 2022, at 16:59:54, Bernd Oppolzer wrote:
>
> The solution LPR ... LCR ... SRL looks OK for me.
> LPR keeps a nonzero result, but with a positive sign,
>
What does this do for an operand of 0x8000?
> LCR does the same, but enforces a negative sign,
>
So the sigh bit
ccpm and carrybit are probably ints or unsigned ints,
because of the L and N instructions, which read them.
so, the & (bitwise AND) operation yields a nonzero result, if there is a
one bit
in the same bit position in both operands. This nonzero result must be
transferred
to a one byte value
Has anyone else seen this?
Yesterday, I applied APAR PH39324 to my HLASM to bring in support for
Z16 machine instructions. I then did a full reassembly of z/XDC (200+
assemblies), and suddenly, out of the blue, 14 of them reported
ASMA500W errors on a DXD instruction that appears in ALL
Thanks John. I appreciate the tips.
Best, Dave
At 4/19/2022 05:53 AM, Jonathan Scott wrote:
Ref: Your note of Tue, 19 Apr 2022 05:48:37 -0400
HLASM now has its own IBM Docs site:
https://www.ibm.com/docs/en/hla-and-tf/1.6
There are links to current PDF documents from that site.
Note
VA takes three vector-register operands; it's VL that takes a storage operand.
I never claimed that HLASM supported quadword integers, just that there were
more than two instructions for quadword binary integer arithmetic.
From: IBM Mainframe Assembler
Noticed today that the GCC C compiler generated an unexpected sequence of
instructions for an AND and TEST:
bool overflow = (ccpm & carrybit) != 0; // check if carry bit set
109 .loc 1 189 0
110 0078 5810B25C l %r1,604(%r11) # D.7949, ccpm
111
Thanks John. That's helpful.
Dave
At 4/19/2022 05:53 AM, Jonathan Scott wrote:
Ref: Your note of Tue, 19 Apr 2022 05:48:37 -0400
HLASM now has its own IBM Docs site:
https://www.ibm.com/docs/en/hla-and-tf/1.6
There are links to current PDF documents from that site.
Note that
Ref: Your note of Tue, 19 Apr 2022 05:48:37 -0400
HLASM now has its own IBM Docs site:
https://www.ibm.com/docs/en/hla-and-tf/1.6
There are links to current PDF documents from that site.
Note that documentation updates mentioned in APAR text may take
some days or weeks to appear in the IBM
I went looking for the PDFs for the High Level Assembler and was
surprised at how hard they were to find...
I started at "z/OS Internet Library"
(https://www-40.ibm.com/servers/resourcelink/svc00100.nsf/pages/zosInternetLibrary?OpenDocument).
From there I selected "V2R3" from "Download books
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