R: R: [Asterisk-Users] E1 PRI problem with TE205P

2006-04-11 Thread Phone Dev
o: Re: R: [Asterisk-Users] E1 PRI problem with TE205P On Mon, 10 Apr 2006 20:24:47 +0200, Phone Dev wrote: > Sorry I forgot, zaptel.conf configuration: > > #Span 1: T1 (channelbank) > span=1,0,0,esf,b8zs > fxoks=1-24 > > #Span 2: E1 PRI > span=2,0,0,ccs,hdb3,crc4 span=2,1

R: [Asterisk-Users] te110p and interrupts

2006-04-11 Thread Phone Dev
Hi Anton, I'm using a supermicro P4 3GHz P8SCT (Intel E7221 chipset) with TE205P and a TDM04 and I've similar problem. I was using linux 2.6.9smp that seams to have problem with APCI so Hyperthreading, even if enabled, was not working (I sow 1 cpu). Today I've disable hypertrading and start using m

R: [Asterisk-Users] E1 PRI problem with TE205P

2006-04-10 Thread Phone Dev
hannel of span 2 Changing configuration to span=2,0,0,ccs,hdb3,crc4 All seams to work (exept for random dropped calls). May this be the cause ? Thanks, Simone -Messaggio originale- Da: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Per conto di Phone Dev Inviato: lunedì 10 aprile

[Asterisk-Users] E1 PRI problem with TE205P

2006-04-10 Thread Phone Dev
Hi all, I've setup a PBX in production environment last week but we have immediatly find out drop conversations and lot of errors (in asterisk logs) like: Apr 10 17:30:48 NOTICE[25154] chan_zap.c: PRI got event: HDLC Bad FCS (8) on Primary D-channel of span 2 My configuration is: Mother

R: [Asterisk-Users] php agi configuration issue

2006-02-06 Thread Phone Dev
You may configure level (verbosity) of login in logger.conf file. In file head some help. Hi, Simone -Messaggio originale- Da: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Per conto di [EMAIL PROTECTED] Inviato: lunedì 6 febbraio 2006 17.45 A: Asterisk Users Mailing List - Non-Comm

[Asterisk-Users] TE210P mother board

2006-02-06 Thread Phone Dev
Hi all, I’m going to configure a middle asterisk installation. I’ll use a TE210P to connect a T1 channel bank and a PRI E1 line. I’m thinking on using a SuperMicro P8SCT Mother Board that has a 1x 64-bit 133MHz PCI-X 3.3V.   In TE210P documentation I’ve read: The TE210P is a 32-bit 33M