On Wed, 27 Apr 2005, Adam Goryachev wrote:
Just wondering, but does the AMD multi CPU architecture improve the
interrupt handling? My understanding of that architecture is that each
CPU can deal with it's own PCI bus/interrupts/etc independently of
each other, and also with their own
Initially, I believed that the limitation was the PCI bus, but I was
mistaken. There is a lot of confusion surrounding this issue, and it
would be great if someone stepped forward with a concrete answer. That
said, here's what I've learned about the issue through my research.
We started off
] Digium Quad Span Cards
Initially, I believed that the limitation was the PCI bus, but I was
mistaken. There is a lot of confusion surrounding this issue, and it
would be great if someone stepped forward with a concrete answer. That
said, here's what I've learned about the issue through my
On Tue, 2005-04-26 at 12:58 -0400, Matt Roth wrote:
So it looks like processor interrupts are the culprit.
Possible solutions to this problem include (please feel free to add to
this list):
- An Asterisk slave server pool (
http://home.comcast.net/~mroth01/LargeAsteriskSetup.gif )
- A
On Apr 26, 2005, at 9:36 PM, Adam Goryachev wrote:
Just wondering, but does the AMD multi CPU architecture improve the
interrupt handling? My understanding of that architecture is that each
CPU can deal with it's own PCI bus/interrupts/etc independently of
each other, and also with their own
From what I understand (and this could be completely wrong), the Digium
cards use a bunch of processor interrupts and too many cards will use up all
the interrupts. (again, that could be completely wrong).
What kind of calls are they? G711-PRI? Not much CPU needed there. G729 -
PRI? Yes, you
