It appears that AR5K_PROFCNT_CYCLE is the register for the on-chip clock. It
is a 32-bit value. When it overflows, it bit shifts right. I use the AR5212
chipset, so I'm not sure if this is the same for you.
- Miklos
On Wed, Jun 9, 2010 at 6:05 PM, Bruno Randolf b...@einfach.org wrote:
On
Hello,
I running some tests with Ath5k in infrastructure mode.
In a scenario when there are a lot of collisions at the AP, the
AR5K_PROFCNT_CYCLE, AR5K_PROFCNT_RXCLR, AR5K_PROFCNT_TX registers all reset
to 0.
I have disabled ANI in these scenarios because it itself resets these
registers.
On Thu, Jun 10, 2010 at 01:04:19PM +0900, Bruno Randolf wrote:
great!
So the following patch takes care of the reset part. I only boot-tested
it so far.
(hmm, tasklet_disable() might actually
do that indirectly, I think).
i dont think so. it just waits for the tasklet to finish and
