[ath5k-devel] need explanation for ath5k tx interrupts

Hi, Can someone kindly explain to me the meaning to the following interrupts found in ATH5K? 1) AR5K_INT_TXEOL 2) AR5K_INT_TXDESC Whenever I send a packet, TXEOL will be raised shortly after transmission, is this interrupt an indication of completion of transmission i.e. last bit of packet ha

Re: [ath5k-devel] ath5k Register Question

Le 30/06/2010 05:44, Jono a écrit : > Hi, > > I'm not sure if this is the right place to ask, but I'm looking for > information on a specific register on Atheros cards. > > I've been told that there is a register that Atheros chips update with > information about how much of a set period has been d

[ath5k-devel] Does ath5k/9k work on 64 bit OSs and machines?

Hi, I am using atth5k/9k driver extensively for my project work. Currently I run it on the 32-bit Lucid Lynx OS on a 32-bit Intel processor. Im thinking of purchasing a new computer and the newer processors these days are all 64 bits. I was wondering if anyone has experienced any problems inst

[ath5k-devel] ath5k Register Question

Hi, I'm not sure if this is the right place to ask, but I'm looking for information on a specific register on Atheros cards. I've been told that there is a register that Atheros chips update with information about how much of a set period has been detected as 'CCA' time. Unfortunately, I cannot f

[ath5k-devel] ath5k Register Question

Hi, I'm not sure if this is the right place to ask this, but I'm looking for information on a specific register on Atheros cards. I've been told that there is a register that Atheros chips update with information about how much of a set period has been detected as 'CCA' time. Unfortunately, I can

Re: [ath5k-devel] Problem about the "done" bit in the descriptor && the bail caused by rxdp value

On Tue, Jun 29, 2010 at 8:32 AM, Bruno Randolf wrote: > On Tue June 29 2010 00:56:48 you wrote: > > Today, i found that there would be only 1000 RXOK interrupt occured, > that's > > why only 1000 packets received. I suspected that it 's because the > latency > > of VxWorks jobQueue is much more t

Re: [ath5k-devel] [ath5k-users] Does ath5k/9k work on 64 bit OSs and machines?

On Tue, 2010-06-29 at 11:08 -0400, Aditya Bhave wrote: > Hi, > > I am using atth5k/9k driver extensively for my project work. Currently I > run it on the 32-bit Lucid Lynx OS on a 32-bit Intel processor. Im > thinking of purchasing a new computer and the newer processors these > days are all 64

[ath5k-devel] [ath5k-users] Does ath5k/9k work on 64 bit OSs and machines?

I'm using mine on a 64 bit host. There have been some issues, but nothing that I would guess has anything to do with the 64-bit:ness. ___ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel

Re: [ath5k-devel] Half/Quarter Channel Support

Hello Benoit, Regarding the Half/Quarter channel support in madwifi-free; does it also implement possible changes in the center frequency ? Is that possible to select different center frequencies? e.g. for quarter channels in 802.11a use channels 37, 38 and 39, ... If not, what sho

Re: [ath5k-devel] Half/Quarter Channel Support

On 06/28/2010 12:17 AM, Benoit Papillault wrote: > Le 25/06/2010 22:08, Steve Brown a écrit : >> >> I see that there are some TO DO comments in the ath5k code for >> half/quarter channels. Is this being worked on? >> >> If not and somebody on the list has the needed info and would be willing >> to

Re: [ath5k-devel] Send packet from inside ath5k_intr() or ath5k_tasklet_rx()

On Wed, Jun 23, 2010 at 1:32 AM, Bob Copeland wrote: > On Tue, Jun 22, 2010 at 3:21 AM, Jin YunYe wrote: >> Thanks for your reply, Bob. >> >> My problem is not exactly compatibility of hardware. Instead, I want >> the driver to send out the response as soon as it receives a packet >> (when notifi