.. you just have to ask the right question. :) half and quarter rates simply clock the chip at half or quarter the normal clock rate. Everything runs at a slower speed and you end up with your reduced bandwidth.
There are some tricks to it. Felix is the best person to describe it to you. There are other concerns too. I don't know if half/quarter rates are supported on _all_ chips - even if the support is there, the chip may have not been marketed as half/quarter rate, so there may be some missing filters or such on the chip itself. HTH, Adrian On 16 July 2012 17:49, John Clark <jcl...@metricsystems.com> wrote: > Does any one know how the 5 and 10 Mhz bandwidth options work? > > This is not 5 Mbits of 'transfer rate', but the bandwidth utilized for > transmitting the > digital signal. > > Since Atheros has been gobbled up by Qualcomm, the ever 'mum' Atheros on > technical details > has become a black hole of nothingness. > > I actually would like to know about the ar9k and the ability of that chip set > to do narrow > bandwidth operations, but that's even a darker subject than > what is to be found in the ar5k code... at least in the ar5k there's code > that seems to > indicate that it supports 5 and 10 Mhz bandwidths. > > Thanks > John Clark. > > _______________________________________________ > ath5k-devel mailing list > ath5k-devel@lists.ath5k.org > https://lists.ath5k.org/mailman/listinfo/ath5k-devel _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel
