Hi,
What register value are you asking about? Which register, and which
value is being written to which register?
Adrian
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> So there are two error counters which count PHY errors. The mask
> register controls which events trigger that counter.
> So AR_PHY_ERR_1 is counter 1, AR_PHY_ERR_MASK_1 is the mask regiser
> for AR_PHY_ERR_1 which controls which PHY errors increment that
> counter.
> Same for _2.
>
Okay.
My ques
Hi,
So there are two error counters which count PHY errors. The mask
register controls which events trigger that counter.
So AR_PHY_ERR_1 is counter 1, AR_PHY_ERR_MASK_1 is the mask regiser
for AR_PHY_ERR_1 which controls which PHY errors increment that
counter.
Same for _2.
Hm, they're in differ
hi,
I checked out the code ...
Its the same code which executes in two different contexts of each radio.
radio 1 has all the values (ofdm, cck)
while radio 0 has ofdm only. cck =0. I couldn't find out where exactly the
difference lies (might be in hardware ? )
There is one other thing :
There are
Hi,
So look at how those values are incremented.
* THey may be incremented from AR_PHY_CNT_{1,2} - see how that's setup
in ani.c and ar5008_phy.c
* They may be incremneted based on RX PHY errors in RX descriptors -
that's enabled by AR_PHY_ERR which is a bitmask of which phy errors to
pass throug
On Thu, May 10, 2012 at 6:49 PM, abhinav narain
wrote:
>
>> "one CCK counter" ? Which registers are you looking at? Or which value?
>> are you looking at the AR_PHY_ERR_CNT_1/ AR_PHY_ERR_CNT_2 registers,
>>
> I am making it simple by taking the values in ath_rx_tasklet()
> from
> ah->stats.ast_ani
>
>
> "one CCK counter" ? Which registers are you looking at? Or which value?
> are you looking at the AR_PHY_ERR_CNT_1/ AR_PHY_ERR_CNT_2 registers,
>
I am making it simple by taking the values in ath_rx_tasklet()
from
ah->stats.ast_ani_ofdmerrs , ah->stats.ast_ani_cckerrs
accumulators
I see al
Hi,
On 9 May 2012 12:13, abhinav narain wrote:
> hi,
>
> I am looking at the hardware counters for PHY ERRS in driver.
> The OFDM counters are incremented as usual, but only one CCK counter is
> incremented
> (for one interface phy0 i suppose) and the other is always 0.
"one CCK counter" ? Which
hi,
I am looking at the hardware counters for PHY ERRS in driver.
The OFDM counters are incremented as usual, but only one CCK counter is
incremented
(for one interface phy0 i suppose) and the other is always 0.
Seeing at the code in ani.c, it looks symmetric for ofdm,cck ... and I
can't figure o
