Even more interesting, though not on the near-term research,
is self-modification.
Lisp code is classically able to self-modify. With this
architecture, the FPGA can self-modify.
The real problems in the near future involve issues like
the "power wall", where most of the silicon is turned off
to
Camm,
Greetings, as you say...
That would save me a lot of effort. At the moment I've been
targeting FORTH because I have a verilog implementation.
I'm hoping for a "Lisp all the way to the metal". That way I can
move freely between Axiom's SANE implementation, to the RISC-V
hard processor and
Greetings! I take it this discussion pertains to the same platform as
Debian's 'riscv64'. There are virtual machine images which can be run
in emulation, but I have been waiting for a porterbox to become
available to port gcl. I anticipate the linker will just take a few
days.
Take care,
Tim
